"The Atari A to Z" by Mark S Baines Copyright (c) 1998 Mark S Baines All Rights Reserved YOU MUST READ "READ_ME.NOW" BEFORE YOU LOOK AT ANY OF THIS FILE ***************************************************************************** M m Milli. M Mega. MACCEL.PRG An official freeware Atari patch program which accelerates the mouse cursor movement on the screen and also includes a screen blanker or saver. There are various versions, MACCEL3 being the latest. It has to be noted that this program creates a nonstandard cookie jar ID thus breaking Atari's own rules for them. There are better mouse accelerators and screen savers but MACCEL is compact. The program runs from the AUTO folder or from the Desktop to configure it. Machine Synonymous with computer. Machine code Synonymous with assembly code and the object code compiled or assembled for a particular computer. Machine independent A language, technique, format or device capable of being used with or on computers of different type. Machine instruction A machine code instruction. Machine language The binary instructions that a computer understands and uses. Machine-oriented language An assembly language. Machine-readable A form that can be translated by machine into computer bit-patterns, such as magnetic media and MICR documents. Macro In a language or some applications, a word or key sequence that generates a string of characters or instructions that perform a particular task. In a word processor, for instance, the key combination [Alt-A] may be set up to enter the user's address. Magnetic disk See Disk. Magnetic tape A storage medium consisting of plastic tape with a magnetizable coating, now rarely used as main storage except in digital cassette form for backup storage. Magnetizable surface A thin coating of magnetizable particles, such as ferric oxide, bound on a substrate, such as Mylar, plastic or aluminium. Magnetizable surface recording The use of a magnetizable surface to receive, store and output data in bit- pattern form. Data is written to the surface by read/write heads that are coils in which the direction of the electric current can be reversed. Changes in this direction change the orientation of the magnetizable particles on the recording surface in a pattern representing the bit-patterns of the data to be stored. In most systems it is not the direction of the particles which is significant but the spacing in-between the changes or flux transitions. The line along which these transitions occur is called a track. In reading, these flux transitions cause temporary currents to flow in the coil of the head which are analysed to determine their data significance. There are a number of coding methods for representing data. Magneto-optical A term used to describe erasable optical storage devices. Data is recorded on the disk surface using a laser beam to produce a tiny area of reverse magnetism. The data is read by a low-power laser beam where the reverse magnetism causes a slight change in the reflectivity of the disk surface. The effect is reversible so that multiple writes and reads can be made as with a normal disk. Data can be stored at high densities of around 600 Mb per double- sided 5.25 inch optical disk. Magnify To increase the size of an image. Mailbox A storage location on multi-user systems and networks for passing private messages and data from one user to another. Mail merge A word processor function of producing many copies of a letter from a single copy and merging into it, usually from a separate list or a database, a series of addresses and other data thus making each letter personalized. As well as addresses, other text material can be merged into the standard letter, perhaps from an accounts program, invoice or club membership database. Main entry point The place where execution begins in a program. Mainframe A large general-purpose computer with extensive processing, I/O and storage capabilities as opposed to a mini or microcomputer, although the distinction is increasingly becoming obscure. Main processor unit The CPU. Main program The principal program in a group of related programs. Main sequence The sequence of instructions that is the body of the program to which control returns after branching. Main storage That addressable storage of a computer system directly accessible to the CPU (and not part of it) without using input/output channels. It is usually semiconductor memory such as RAM and ROM. Maintenance The activity of altering programs and data to reflect changing procedures and needs and of documenting those changes. Also, keeping hardware in an operational condition. MAKEFAST.PRG An official freeware Atari program which will set the fastload bit on any executable file on disk. This will result in the slightly faster loading of these programs. It is a very simple program and does everything from alerts setting or clearing the fastload bit or checking the state of it. There are other programs now available that can set the various program header flags most of which seem to be called PRGFLAGS! See Fastload bit. Malfunction A fault, usually in hardware. Malloc A GEMDOS function which allocates a block of memory from the GEMDOS free memory pool to the program making the call. See Forty folder bug. Management information system - MIS Programs and techniques designed to provide management with timely data as an aid to decision making. Manipulate To change the form of data or to perform operations on it. Mantissa The fractional part of a number. See Floating point. Manual An operation performed by hand or a product's operational documentation. Map To establish a one-to-one relationship between the entities of different sets. Also, a list of data units and their locations in storage, as in a 'file or memory map'. Marginal Unstable and error-prone equipment likely to fail. Mark A representation of data in an optically detectable non-character form, such as a pencil line in a box. Also, a 1-bit used in transmission of data. Mask A pattern of bits that is used to control which bits of input are to be included in output. Typically, it is a string containing a 1-bit in each bit position where the input is to be moved to output and a 0-bit where it is not. This principle, for instance, determines which foreground object is displayed against a background on a graphics screen, such as the Desktop icons. Masked Sometimes synonymous with disabled. Mass storage Any large storage, typically hard disks and tape over 200 Megabytes, directly accessible to the computer - usually a mainframe or mini. This term is becoming increasingly redundant. Master file That file that is the most up-to-date and authoritative in a system where multiple copies and generations of files exist. Also, the original, purchased commercial software disks rather than their backup copies. Match Comparing items in order to locate those with the same attributes. Matrix An arrangement of items in rows and columns and, possibly, planes each being identified by its coordinates, such as an array or grid for forming dot matrix characters. Matrix character A dot matrix character or character constructed of line segments, as in a LED display. Matrix printer See Dot matrix printer. Mb, MB, Mbyte MegaByte. MC1377P On the ST, a Motorola 1377P chip is used to convert the SHIFTER's RGB signals and the GLUE's sync signals to a composite video output in PAL or NTSC format. This signal is fed to the monitor socket where it can be used to drive a monitor. The signal is also fed to a UHF modulator which converts it into a UHF TV signal. The 1377P also receives a 4.433 MHz colour subcarrier signal from a crystal oscillator which is phase locked with the main 32 MHz crystal. This eliminates colour drifting. See Modulator, RGB. MC146818A The Motorola Real-Time Clock chip with RAM on the TT. See Real-time clock. MC56001 The Motorola DSP chip as fitted to the Falcon030. The 56001 utilizes seven internal buses, of which three are 16-bit address buses and the others are 24- bit data buses. One address bus is used for program instruction fetches and the other two are used for the X and Y operand fetches from on-chip or external RAM. In this way the DSP can pre-fetch the next instruction at the same time as it performs the current instruction on two operands which are both fetched simultaneously. Three data buses are assigned to program, X operand, and Y operand, and the fourth is a general purpose data bus. On-chip there is 32 x 24-bit words of bootstrap ROM, 512 x 24-bit words of program RAM and two areas of 256 x 24-bit RAM - one assigned to the X bus and one to the Y bus. The X bus also has a 256 x 24-bit ROM which is preprogrammed with positive Mu-law and A-law companding tables (useful in telecommunications) and the Y bus has a similar sized ROM preprogrammed with a full four quadrant 24- bit sine table. The X, Y and program RAM areas may be expanded off-chip up to 64 K x 24-bits each. There is a flexible 47-pin I/O expansion port and two other ports providing another 24 I/O pins if required although these are configurable. The host interface is via a byte-wide full duplex parallel port with full DMA support. The full duplex serial synchronous/asynchronous communications interface can communicate at up to 2.5 Mbps and a second synchronous serial interface is provided for inter-chip communications. Each interface has its own (maskable) interrupt vector addresses. The heart of the DSP consists of an ALU, an AGU (address generator) and the program controller. Speed is rated at 10.25 MIPS. It can execute a 1,024-point complex fast Fourier transform in 3.23 milliseconds. The instruction set consists of 62 MCU-like instruction mnemonics, many being similar to MC68000 family mnemonics. A hardware DO loop instruction and a repeat (REP) instruction are also available. See DSP. MC68000 The Motorola MC68000 16-bit microprocessor has a 32-bit internal and 16-bit external data bus, with a 24-bit address bus enabling its direct linear access to 16 Mb of memory. The usual clock frequency is 8 MHz as fitted to the ST range although 12 and 16 MHz varieties exist. The Mega STE has a 16 MHz 68000 and third party upgrades can push the speed to 36 MHz giving a practical speed increase of three times over an 8 MHz ST. The 68000 has eight 32-bit data registers and seven 32-bit address registers. There are two 32-bit stack pointers, one 32-bit program counter and a 16-bit status register. Its name derives from the fact that it consists of around 68,000 transistors. The MC68000 features 56 basic instructions where operations can be based on bits, bytes, words or long words. There are two modes of operation, 'user' and 'supervisor', the former checking for an operation's memory access ensuring the program is keeping out of the protected memory thus preventing its possible corruption. The latter allows access to this memory but requires a conscious effort on the part of the programmer to do so. The 68000 can control both synchronous and asynchronous devices and it reserves the first 1,024 bytes where the exception table is located. Most early 68000s are housed in a 64-pin DIL package although lately they appear in the square 68-pin PLCC sockets and are powered through +5 V and 0 V pins. CMOS varieties are available. MC68020 Launched in 1984, the Motorola 68020 never featured in any Atari computers. It is a full 32-bit device capable of addressing 4 Gb of memory like the 68030. It has a greatly enhanced instruction set, an on-chip 256-byte instruction cache and an interface for floating point coprocessors, such as the MC68882. Pipelining was introduced to speed up some operations which handles up to three instructions at once by splitting their execution into three stages. MC68030 The Motorola 68030 microprocessor was launched in 1987 and is fitted in the TT and Falcon030 running at 32 MHz in the TT and 16 MHz in the Falcon. It is reputed to consist of 300,000 transistors. Apart from its faster clock speed, it is superior to the 68000 in having a full 32-bit data bus, a 32-bit address bus (giving a direct, linear memory space of 4 Gb), internal data and instruction caches (256 bytes each), pipelining, dynamic bus sizing (access to odd as well as even addresses), a more efficient microcode and hardware memory protection and management enabling safe and efficient multitasking. Burst mode transfers of data allows the reading of four 32-bit long words in just five clock cycles and the internal architecture allows data and instructions to move within the chip on separate buses concurrently. MC68040 Launched in 1990, this Motorola processor was not used by Atari. It is rated at 29 MIPS with a 33 MHz clock and contains 1.2 million transistors. The internal data and instruction caches are now 4 K each (which Motorola claim to have a 99% hit rate) and burst mode writes are also available. It can operate at 32 MHz or faster (40 MHz is the fastest available at the time of writing) and has an integrated FPU on-chip delivering 3.5 MFLOPS. Extensive pipelining and the hard wiring of certain key operations result in an average execution time of 1.25 clock cycles per instruction compared to 1.9 for an Intel 80486. Up to fourteen operations can be processed at once. The FPU can perform three activities at once in parallel with the integer unit which can perform six operations at once and the internal caches have their own memory management units giving the 68040 extensive parallelism capabilities. Unlike the MC68020 and MC68030 processors, the MC68040 does not support dynamic bus sizing and expects the referenced device to be able to accept the requested access width. Blocks of memory which must be contiguous, such as code storage or program stacks, must be 32 bits wide. MC68050 The release of this chip was supposed to have been in 1992 but Motorola decided to drop it in favour of waiting for the 68060 in 1994. The reason for this is unclear although it is likely that Motorola didn't see a market for it when the 68060 was so near to finishing. The 68050 was also not fast enough to compete with the Intel Pentium (P5 or 80586 as it was originally known) which was soon to emerge. The 68050 was to have the facility of connecting several in parallel with each other. This was carried forward to include a new series of MMU chips and slave processors. MC68060 The 68060 was released in 1994 and is a 32-bit processor with a superscalar, pipelined architecture which means it can perform two instructions per clock cycle. It has a 64-bit data bus, a 32-bit address bus and 32-bit registers. It has more than two million transistors, using a 0.5 micron, triple-layer metal, 3.3 volt process in a static design. Performance will be 3.5 times that of the 25 MHz 68040, or about 46 SPECmarks, 100 MIPS and 12 MFLOPS according to Motorola although these may well be based on very optimized tests. Byte magazine claims about 77 MIPS. Separated in the 68060 are instruction caches and data caches; instruction fetch pipelines (with four-stage instruction processor, a physically-mapped 8 K instruction cache with four-way self associative, a virtually mapped 256- entry branch cache and a FIFO instruction buffer), and operand execution pipelines (with four-stage operand processor, a physically mapped 8 K data cache with 4-way interleaving and a 4-entry, 32-bit write buffer). The floating point unit - implemented in the execution stage of the operand execution pipeline - is compatible with the 68040 FPU programming model. Floating point execution times range from 1-24 cycles. The 68060 superscalar dispatch algorithm can execute 50 to 60 percent of integer code instructions as pairs with existing compilers. The 68060 comes in a 68040-style package with a similar external bus and runs at 50 MHz and 66 MHz. MC6850 See ACIA. MC68851 Motorola memory management processor which is the basis of the MMU chip on the ST and TT. MC68881 Motorola floating point coprocessor. Originally fitted to some TTs and standard on a Mega STE and optional on a Falcon030. Also optional on a Mega ST with the SFP004 expansion board. The MC68881 appears as a peripheral input/output port in the memory map of the Mega ST and STE as the MC68000 CPU does not support coprocessors, which makes the operation of the MC68881 slower, but still faster than if one wasn't fitted. The MC68030 can properly support a coprocessor. See FPU and SFP004. MC68882 Motorola floating point coprocessor, fitted to the TT as standard and optional on the Mega STE and Falcon. It is essentially the same as a MC68881 but performs its calculations about 1.5 times faster than it. See MC68881, FPU. MC68901 See MFP 68901. MC68LC040 This is basically a Motorola 68040 without the FPU, thus making it cheaper than a 68040 but just as fast for non-floating point operations, which only a few programs support on the ST-Falcon anyway. MCA Micro Channel Architecture. The expansion bus connector developed by IBM on the PS/2 range of computers allowing for daughter boards to be plugged into the motherboard. The royalty imposed on this design caused other manufacturers to develop the more widespread EISA system. MCGA Multi-Colour Graphics Array. A screen display system used on some IBM PS/2 computers to provide CGA graphics made necessary because the PS/2 range used analogue monitors and CGA was designed for RGB TTL monitors. MCU Memory Control Unit. Atari custom chip in the STE and TT which works like the ST MMU and GLUE chips and replaces them on the motherboard. It comes as a 144- pin gullwing surface mounted device. The MCU controls the memory, ROM access, floppy clock selection, real-time clock access and video sync generation. The 68030 of the TT and Falcon030 does its own memory management and protection so many of the functions of the ST's MMU are not needed although separate MMUs are required for each expansion board of memory. See GLUE, MMU. MDA Monochrome Display Adaptor. An early form of screen display used by IBM PC compatibles capable of displaying 80 x 25 text displays using a character matrix of 9 x 14 dots. It is hardly used any more. Mean Synonymous with average. Media conversion Transcription of data from one storage medium to another, say from tape to disk. Medium A physical means used to represent data for storage or transfer, such as the magnetizable surface of a disk. Medium scale integration - MSI Semiconductor devices with ten to a hundred gates per chip. Medium resolution The ST's four colour display of 640 x 200 pixels. Medium speed A data transmission speed of between 2,400 and 4,800 bits per second. Mega - M Prefix meaning one million (10^6). Megabyte - MB, Mb, Mbyte A 'computer million' (2^20) or 1,048,576 bytes. MegaFile 20 Atari 20 Mb hard disk drive in a Mega ST type case. MegaFile 30 Atari 30 Mb hard disk drive in a Mega ST type case, using RLL encoding with a transfer rate of 5 Mbits per second and an average access time of 65 ms. MegaFile 44 Atari 44 Mb removable cartridge drive based on a SyQuest mechanism in a Mega ST type case. MegaFile 60 Atari 60 Mb hard disk drive in a Mega ST type case using RLL encoding with a transfer rate of 5 Mbits per second and an average access time of 65 ms. Megahertz - MHz A frequency of one million (10^6) cycles per second. Mega ST Atari's 'three-box' version of the ST with separate keyboard, BLiTTER, real- time clock and internal MC68000 bus connector for a single expansion card. Running with an 8 MHz MC68000 processor, it is now dated compared to its companions and was replaced by the Mega STE in 1991/2. Table M1: Mega ST Specification Processor 8 MHz MC68000 8 MHz BLiTTER DMA Bus 16-bit external data, 32-bit internal data, 24-bit address RAM 1, 2 or 4 Mb ROM 2 or 6 sockets providing 192 K of ROM space Floppy Disk Drive 3.5" double-sided double density 720 K Input/Output MIDI in and out (5-pin DIN) Monitor port (13-pin DIN) for ST monochrome or colour monitors Parallel printer port Serial port from MFP 68901 (25-pin DB) External floppy disk (14-pin DIN) Atari ACSI connector with DMA (19-pin DB) ST compatible cartridge port (128 K) Keyboard input Internal bus expansion port (64-pin) Video Colour palette of 512 colours 320 x 200 x 16 colours ST low resolution 640 x 200 x 4 colours ST medium resolution 640 x 400 monochrome ST high resolution Text display 80 columns (high resolution) or 40 columns (low resolution) x 25 lines Sound 3 channel PSG sound Total MIDI compatibility Keyboard Separate QWERTY keyboard, 95 keys, numeric keypad, 10 function keys, cursor keys, ST joystick (9-pin DB) and ST mouse (9-pin DB) ports Mouse 128 dpi 2 button Real-Time Clock Battery backed Power Internal PSU Operating System TOS 1.2 with GEM Desktop in ROM (upgradeable to TOS 1.4) Mega STE Development of the STE into a 'three-box' design based on the TT case but in Atari 'grey'. It is very similar to a TT using a 16 MHz 68000 CPU with 32 K RAM cache (instead of a MC68030), a BLiTTER and an optional 16 MHz 68881 floating point coprocessor. It has the ST's video resolutions. The MC68000 can be optionally switched to 8 MHz for backwards compatibility and the RAM cache turned off. Like the TT, it has a LAN interface, three serial ports, VME and ACSI ports in addition to the STE's stereo sound output sockets. Memory is 1, 2 or 4 Mb with a 48 Mb or 80 Mb built-in hard disk (optional on 1 Mb version) and a TV modulator is a surprise addition. TOS 2 is used with the NewDesk Desktop. It does not have the Mega ST 68000 internal expansion bus and the STE's digital/analogue controller ports. The Mega STE replaced the Mega ST and is seen to fill the small business and serious home enthusiast niche. Table M2: Mega STE Specification Processor 16 MHz MC68000 32 K RAM Cache (switchable to 8 MHz) 16 MHz MC68881 FPU (optional) 8 MHz BLiTTER DMA Bus 16-bit external data, 32-bit internal data, 24-bit address RAM 1, 2 or 4 Mb ROM 2 sockets providing 256 K of ROM space Hard Disk Drive Internal SCSI 48 Mb or 80 Mb (optional with 1 Mb, sizes change with availability) Floppy Disk Drive 3.5" double-sided high density 1.44 Mb Input/Output MIDI in and out (5-pin DIN) Monitor port (13-pin DIN) for ST monochrome or colour monitors RF modulator output for TV (colour resolutions only) Parallel printer port 2 asynchronous serial ports from two MFP 68901 (9-pin DB) 1 high-speed SCC serial port (9-pin DB) SCC LAN with DMA (8-pin mini-DIN) Atari ACSI with DMA External floppy disk drive interface ST compatible cartridge port (128 K) Separate keyboard interface 2 stereo sound output RCA-style phono sockets Internal VME card slot (A24/D16 and A16/D16 slave only) Video Colour palette of 4,096 colours 320 x 200 x 16 colours ST low resolution 640 x 200 x 4 colours ST medium resolution 640 x 400 monochrome ST high resolution 80 column text display (40 in low resolution) Colour modes 50-60 Hz, monochrome 71.4 Hz Sound Total MIDI compatibility Stereo 8-bit PCM DMA sound (STE compatible) 3 channel PSG sound (ST compatible) Internal mono speaker (which can be disabled) Keyboard Separate QWERTY keyboard, 95 keys, numeric keypad, 10 function keys, cursor keys, mouse port (9-pin DB), joystick port (9-pin DB) Mouse 128 dpi 2 button Real-Time Clock Battery backed RTC with 50 bytes of non-volatile RAM Power Internal PSU Operating System TOS 2.0x with GEM and NewDesk Desktop in ROM Member A unit that makes up a group. In a hierarchy, an element that is lower or controlled by another, as in databases where records are members of files. Memory A medium or device capable of receiving, retaining and outputting data in binary form, often used to refer to semiconductor memory such as RAM or ROM. Memory cell A single bit-sized storage cell. Memory form definition block - MFDB A VDI programming data structure concerned with VDI raster operations (screen graphics). Memory map - ST/STE The first 2,048 ($00000000-$000007FF) bytes of ST memory are reserved for the exception vectors and system variables. The first eight bytes of the ROM are shadowed at the start of RAM for the reset stack pointer and program counter. This area along with I/O space at $00FF8000 is protected for supervisor references only. Accessing supervisor protected areas while in the user state will result in a bus error. Writing to this area or any ROM location will also result in a bus error. The following is a map of ST/STE memory (including Mega ST and Mega STE). Addresses are in hexadecimal. Table M3: General Memory Map - ST/STE Address Use 00000000 ROM Supervisor stack pointer 00000004 ROM Program counter 00000008 RAM Exception vectors 00000400 RAM System variables 00000800 RAM Main RAM start 003FFFFF RAM End of maximum physical RAM space 00400000 RAM May be used by hardware developers 00A00000 VME/ Mega STE VME A24:D16 address space or additional 00DEFFFF RAM ST compatible RAM or I/O space for Mega STE 00C00000 RAM Expansion bus memory (Mega ST) 00CFFFFF RAM End of expansion bus memory (Mega ST) 00DF0000 VME/ Mega STE VME A16:D16 address space or additional 00DFFFFF RAM ST compatible RAM or I/O space for Mega STE 00E00000 ROM Main system ROM space for TOS 1.6 onwards 00EFFFFF ROM End of system ROM space for TOS 1.6 onwards 00F00000 reserved 00FA0000 ROM Cartridge ROM space 00FC0000 ROM Main system ROM space for TOS 1.0-1.4 00FEFFFF ROM End of system ROM space for TOS 1.0-1.4 00FF0000 reserved 00FF8001 I/O Memory controller register 00FF8002 unassigned 00FF8200 I/O Video controller registers 00FF8266 unassigned 00FF8600 I/O ACSI DMA and FDC registers 00FF860E unassigned 00FF8800 I/O Programmable sound chip registers 00FF8804 unassigned 00FF8900 I/O STE DMA sound registers 00FF8922 I/O STE MICROWIRE registers 00FF8926 unassigned 00FF8960 I/O Mega STE real-time clock registers 00FF8964 unassigned 00FF8A00 I/O BLiTTER registers 00FF8A3E unassigned 00FF8C80 I/O Mega STE SCC ports registers 00FF8C88 unassigned 00FF8E00 I/0 Mega STE VME system control unit (SCU) registers 00FF8E10 unassigned 00FF8E21 I/O Mega STE cache/processor control 00FF8E22 unassigned 00FF9200 I/O Mega STE configuration switches 00FF9200 I/O STE extended joystick controllers registers 00FF9224 unassigned 00FFFA00 I/O MFP 68901 registers 00FFFA30 unassigned 00FFFA40 I/O Mega ST/Mega STE 68881 FPU peripheral registers 00FFFA54 unassigned 00FFFC00 I/O Keyboard and MIDI ACIA registers 00FFFC20 I/O Mega ST real-time clock registers 00FFFC40 unassigned 00FFFFFF End of address space Memory map I/O - ST/STE The ST/STE input/output space is at $00FF8000 to $00FFFFFF. Accessing reserved I/O addresses will result in a bus error. The following is a map of ST/STE I/O space, where RW = Read/Write, RO = Read Only, WO = Write Only, 'x' marks a valid bit position in the byte or word and '-' marks an unused bit which is always assumed to have a value of zero. Each address shows a word or sixteen bits, the even (high) byte being on the left and the odd (low) byte on the right. Addresses are in hexadecimal. Table M4: Memory Controller Register FF8000 RW ---- ---- ---- xxxx Memory configuration Bank0 Bank1 0000 128 K 128 K 0001 128 K 512 K 0010 128 K 2 Mb 0011 Reserved 0100 512 K 128 K 0101 512 K 512 K 0110 512 K 2 Mb 0111 Reserved 1000 2 Mb 128 K 1001 2 Mb 512 K 1010 2 Mb 2 Mb 1011 Reserved 11xx Reserved Table M5: ST Video Controller Registers FF8200 RW ---- ---- xxxx xxxx Video base high FF8202 RW ---- ---- xxxx xxxx Video base low FF8204 RO ---- ---- xxxx xxxx Video address counter high FF8206 RO ---- ---- xxxx xxxx Video address counter middle FF8208 RO ---- ---- xxxx xxxx Video address counter low FF820A RW ---- --xx ---- ---- Video sync mode ||___________ External/internal sync |____________ 50/60 Hz field rate FF8240 RW ---- -xxx -xxx -xxx Palette colour 0 and border | | ||_ Inverted/normal monochrome | | |__ Blue | |_______ Green |____________ Red to FF825E RW ---- -xxx -xxx -xxx Palette colour 15 FF8260 RW ---- --xx ---- ---- Shift mode 00 320 x 200, 4 planes 01 640 x 200, 2 planes 10 640 x 400, 1 plane 11 Reserved FF827E R/W ---- -xx- ---- ---- Stacy display state ||____________ Display on/off |_____________ Backlight on/off Table M6: STE Video Controller Registers FF8200 RW ---- ---- --xx xxxx Video base high FF8202 RW ---- ---- xxxx xxxx Video base middle FF8204 RW ---- ---- xxxx xxxx Video address counter high FF8206 RW ---- ---- xxxx xxxx Video address counter middle FF8208 RW ---- ---- xxxx xxxx Video address counter low FF820A RW ---- --xx ---- ---- Sync mode ||___________ External/internal sync |____________ 50/60 Hz field rate FF820C RW ---- ---- xxxx xxxx Video base low FF820E RW ---- ---- xxxx xxxx LINEWID register FF8240 RW ---- 0321 0321 0321 Palette colour 0 and border | | | |_ Inverted/normal monochrome | | |___ Blue | |________ Green |_____________ Red to FF825E RW ---- 0321 0321 0321 Palette colour 15 FF8260 RW ---- --xx ---- ---- Shift mode 00 320 x 200, 4 planes 01 640 x 200, 2 planes 10 640 x 400, 1 plane 11 Reserved FF8264 RW ---- ---- ---- xxxx HSCROLL register Table M7: ACSI DMA and FDC Registers FF8600 ---- ---- ---- ---- Reserved FF8602 ---- ---- ---- ---- Reserved FF8604 RW ---- ---- xxxx xxxx FDC access/sector count FF8606 RO ---- ---- ---- -xxx DMA status |||_ Error status ||__ Sector count zero status |___ Data request inactive status FF8606 WO ---- ---x xxxx xxx- DMA mode control | |||| |||__ A0 | |||| ||___ A1 | |||| |____ HDC/FDC register select | ||||______ Sector count register select | ||0 Reserved | ||________ Disable/enable DMA | |_________ FDC/HDC access |___________ Write/read FF8608 RW ---- ---- xxxx xxxx DMA base and counter high FF860A RW ---- ---- xxxx xxxx DMA base and counter middle FF860C RW ---- ---- xxxx xxxx DMA base and counter low Table M8: Programmable Sound Chip Registers FF8800 RO xxxx xxxx ---- ---- PSG read data |||| |||| I/O port B ||||_||||___________ Parallel interface data FF8800 WO ---- xxxx ---- ---- PSG register select ||||___________ Register number 0000 Channel A fine tune 0001 Channel A coarse tune 0010 Channel B fine tune 0011 Channel B coarse tune 0100 Channel C fine tune 0101 Channel C coarse tune 0110 Noise generator control 0111 Mixer control - I/O enable 1000 Channel A amplitude 1001 Channel B amplitude 1010 Channel C amplitude 1011 Envelope period fine tune 1100 Envelope period coarse tune 1101 I/O port A select (output only) 1111 I/O port B select FF8802 WO xxxx xxxx ---- ---- PSG write data |||| |||| I/O port A |||| ||||___________ Floppy side 0/side 1 select |||| |||____________ Floppy drive 0 select |||| ||_____________ Floppy drive 1 select |||| |______________ RS-232 request to send ||||________________ RS-232 data terminal ready |||_________________ Printer port STROBE ||__________________ General purpose output |___________________ Reserved |||| |||| I/O port B ||||_||||___________ Parallel interface data Table M9: STE DMA Sound Control Registers FF8900 RW ---- ---- ---- --xx Sound DMA control 00 Sound DMA disabled 01 Sound DMA enabled 11 Enabled, repeat frame forever FF8902 RW ---- ---- --xx xxxx Frame base address high FF8904 RW ---- ---- xxxx xxxx Frame base address middle FF8906 RW ---- ---- xxxx xxxx Frame base address low FF8908 RO ---- ---- --xx xxxx Frame address counter high FF890A RO ---- ---- xxxx xxxx Frame address counter middle FF890C RO ---- ---- xxxx xxxx Frame address counter low FF890E RW ---- ---- --xx xxxx Frame end address high FF8910 RW ---- ---- xxxx xxxx Frame end address middle FF8912 RW ---- ---- xxxx xxxx Frame end address low FF8920 RW ---- ---- x--- --xx Sound mode control 00 6,258 Hz sample rate 01 12,517 Hz sample rate 10 25,033 Hz sample rate 11 50,066 Hz sample rate 0 Stereo mode 1 Mono mode Table M10: STE MICROWIRE Registers FF8922 RW xxxx xxxx xxxx xxxx MICROWIRE data register FF8924 RW xxxx xxxx xxxx xxxx MICROWIRE mask register Table M11: Mega STE Real-Time Clock Registers FF8960 RW ---- ---- xxxx xxxx Address register FF8962 RW ---- ---- xxxx xxxx Data register Table M12: BLiTTER Registers FF8A00 RW xxxx xxxx xxxx xxxx Half-tone RAM row 0 to FF8A1E RW xxxx xxxx xxxx xxxx Half-tone RAM row 15 FF8A20 RW xxxx xxxx xxxx xxxx Source X increment FF8A22 RW xxxx xxxx xxxx xxxx Source Y increment FF8A24 RW ---- ---- xxxx xxxx Source address high FF8A26 RW xxxx xxxx xxxx xxx0 Source address low FF8A28 RW xxxx xxxx xxxx xxxx Endmask 1 FF8A2A RW xxxx xxxx xxxx xxxx Endmask 2 FF8A2C RW xxxx xxxx xxxx xxxx Endmask 3 FF8A2E RW xxxx xxxx xxxx xxxx Destination X increment FF8A30 RW xxxx xxxx xxxx xxxx Destination Y increment FF8A32 RW ---- ---- xxxx xxxx Destination address high FF8A34 RW xxxx xxxx xxxx xxx0 Destination address low FF8A36 RW xxxx xxxx xxxx xxxx X-count FF8A38 RW xxxx xxxx xxxx xxxx Y-count FF8A3A RW ---- --xx Half-tone operation (HOP) 00 All 1-bits 01 Half-tone RAM 10 Source 11 Source and half-tone RAM FF8A3B RW ---- xxxx Logical operation (OP) 0000 All 0-bits 0001 Source AND destination 0010 Source AND NOT destination 0011 Source 0100 NOT source AND destination 0101 Destination 0110 Source XOR destination 0111 Source OR destination 1000 NOT source AND NOT destination 1001 NOT source XOR destination 1010 NOT destination 1011 Source OR NOT destination 1100 NOT source 1101 NOT source OR destination 1110 NOT source OR NOT destination 1111 All 1-bits FF8A3C RW xxx- xxxx xx-- xxxx Configuration ||| |||| || ||||_ SKEW ||| |||| ||________ No final source read (NFSR) ||| |||| |_________ Force extra source read (FXSR) ||| ||||___________ Line number |||_________________ SMUDGE ||__________________ HOG |___________________ Busy Table M13: Mega STE SCC Ports FF8C80 RW ---- ---- xxxx xxxx SCC A control FF8C82 RW ---- ---- xxxx xxxx SCC A data FF8C84 RW ---- ---- xxxx xxxx SCC B control FF8C86 RW ---- ---- xxxx xxxx SCC B data Table M14: Mega STE VME System Control Unit (SCU) Registers FF8E00 RW ---- ---- xxxx xxx- System interrupt mask FF8E02 RO ---- ---- xxxx xxxx System interrupt state FF8E04 RW ---- ---- ---- ---x System interrupter 1 Generate interrupt FF8E06 RW ---- ---- ---- ---x VME interrupter 1 Generate interrupt VME IRQ3 FF8E08 RO ---- ---- xxxx xxxx General purpose register 1 FF8E0A RO ---- ---- xxxx xxxx General purpose register 2 FF8E0C RW ---- ---- xxxx xxx- VME interrupt mask FF8E0E RO ---- ---- xxxx xxxx VME interrupt state Table M15: Mega STE Cache and Processor Control FF8E20 RW ---- ---- ---- --xx Cache/processor control register Table M16: Mega STE Configuration Switches FF9200 RW xxxx xxxx ---- ---- Table M17: STE Game Controllers Registers FF9200 RW ---- xxxx ---- ---- Joystick fire buttons 3210 Controller port number FF9202 RW xxxx xxxx xxxx xxxx Joystick directions UDLR UDLR UDLR UDLR Joy3 Joy1 Joy2 Joy0 Joystick 1 and 3 are RO FF9210 RO ---- ---- xxxx xxxx Paddle 0 X Fire buttons as for joysticks FF9212 RO ---- ---- xxxx xxxx Paddle 0 Y Triggers are JOY 0 left and right FF9214 RO ---- ---- xxxx xxxx Paddle 1 Y FF9216 RO ---- ---- xxxx xxxx Paddle 1 X FF9220 RO ---- --xx xxxx xxxx Light gun/pen X FF9222 RO ---- --xx xxxx xxxx Light gun/pen Y Table M18: MFP 68901 Registers FFFA00 RW ---- ---- xxxx xxxx General purpose I/O GPIP FFFA02 RW ---- ---- xxxx -xxx Active edge AER |||| |||_ Centronics busy |||| ||__ RS-232 carrier detect |||| |___ RS-232 clear to send ||||______ Keyboard/MIDI interrupt |||_______ FDC/HDC interrupt ||________ RS-232 ring indicator |_________ Monochrome monitor detect FFFA04 RW ---- ---- xxxx xxxx Data direction DDR FFFA06 RW ---- ---- xxxx xxxx Interrupt enable A IERA |||| ||||_ Timer B (HBlank counter) |||| |||__ Sender error |||| ||___ Sender buffer empty |||| |____ Receive buffer empty ||||______ Receive buffer full |||_______ Timer A (DMA sound counter) ||________ RS-232 ring indicator |_________ Monochrome monitor detect FFFA08 RW ---- ---- xxxx xxxx Interrupt enable B IERB |||| ||||_ Centronics busy |||| |||__ RS-232 carrier detect |||| ||___ RS-232 clear to send |||| |____ BitBLT complete ||||______ Timer D (baud rate generator) |||_______ Timer C (200 Hz system clock) ||________ Keyboard/MIDI interrupt |_________ FDC/HDC interrupt FFFA0A RW ---- ---- xxxx xxxx Interrupt pending A IPRA mapping as for IERA FFFA0C RW ---- ---- xxxx xxxx Interrupt pending B IPRB mapping as for IERB FFFA0E RW ---- ---- xxxx xxxx Interrupt in-service A ISRA mapping as for IERA FFFA10 RW ---- ---- xxxx xxxx Interrupt in-service B ISRB mapping as for IERB FFFA12 RW ---- ---- xxxx xxxx Interrupt mask A IMRA mapping as for IERA FFFA14 RW ---- ---- xxxx xxxx Interrupt mask B IMRB mapping as for IERB FFFA16 RW ---- ---- ---- x--- Vector VR 0 Automatic end-of-interrupt 1 Software end-of-interrupt FFFA18 RW ---- ---- ---- xxxx Timer A control TACR 0000 Timer stop 0001 Delay mode, divide by 4 0010 Delay mode, divide by 10 0011 Delay mode, divide by 16 0100 Delay mode, divide by 50 0101 Delay mode, divide by 64 0110 Delay mode, divide by 100 0111 Delay mode, divide by 200 1000 Event count mode 1001 Pulse extension mode 1001 Pulse extension mode, divide by 4 1010 Pulse extension mode, divide by 10 1011 Pulse extension mode, divide by 16 1100 Pulse extension mode, divide by 50 1101 Pulse extension mode, divide by 64 1110 Pulse extension mode, divide by 100 1111 Pulse extension mode, divide by 200 FFFA1A RW ---- ---- ---- xxxx Timer B control TBCR mapping as for TACR FFFA1C RW ---- ---- -xxx -xxx Timers C and D control TCDCR 000 Timer C stop 001 Timer C delay mode, divide by 4 010 Timer C delay mode, divide by 10 011 Timer C delay mode, divide by 16 100 Timer C delay mode, divide by 50 101 Timer C delay mode, divide by 64 110 Timer C delay mode, divide by 100 111 Timer C delay mode, divide by 200 000 Timer D stop 001 Timer D delay mode, divide by 4 010 Timer D delay mode, divide by 10 011 Timer D delay mode, divide by 16 100 Timer D delay mode, divide by 50 101 Timer D delay mode, divide by 64 110 Timer D delay mode, divide by 100 111 Timer D delay mode, divide by 200 FFFA1E RW ---- ---- xxxx xxxx Timer A data TADR FFFA20 RW ---- ---- xxxx xxxx Timer B data TBDR FFFA22 RW ---- ---- xxxx xxxx Timer C data TCDR FFFA24 RW ---- ---- xxxx xxxx Timer D data TDDR FFFA26 RW ---- ---- xxxx xxxx Sync character SCR FFFA28 RW ---- ---- xxxx xxx- USART control UCR |||| |||__ Parity |||| ||___ Even/odd parity |||0 0 Synchronous |||0 1 1 stop, 1 start bits |||1 0 1 stop, 1.5 start bits |||1 1 1 stop, 2 start bits |00 8 bits |01 7 bits |10 6 bits |11 5 bits |_________ Clock divide by 16 FFFA2A RW ---- ---- xxxx xxxx Receiver status RSR |||| ||||_ Receiver enable |||| |||__ Synchronous strip enable |||| ||___ Match/character in progress |||| |____ Search/break detect ||||______ Frame error |||_______ Parity error ||________ Overrun error |_________ Buffer full FFFA2C RW ---- ---- xxxx xxxx Transmitter status TSR |||| ||||_ Transmitter enable |||| |||__ Low bit |||| ||___ High bit |||| |____ Break ||||______ End of transmission |||_______ Auto-turnaround ||________ Underrun error |_________ Buffer empty FFFA2E RW ---- ---- xxxx xxxx USART data UDR Table M19: Mega ST/Mega STE 68881 FPU Peripheral Registers FFFA40 RW xxxx xxxx xxxx xxxx FPCIR status register FFFA42 RW xxxx xxxx xxxx xxxx FPCTL control register FFFA44 RW xxxx xxxx xxxx xxxx FPSAV save register FFFA46 RW xxxx xxxx xxxx xxxx FPREST restore register FFFA48 RW xxxx xxxx xxxx xxxx FPOPR operation register FFFA4A RW xxxx xxxx xxxx xxxx FPCMD command register FFFA4C RW xxxx xxxx xxxx xxxx FPRES reserved FFFA4E RW xxxx xxxx xxxx xxxx FPCCR condition code register FFFA50 RW xxxx xxxx xxxx xxxx FPOP operand register high FFFA52 RW xxxx xxxx xxxx xxxx FPOP operand register low FFFA54 RW xxxx xxxx xxxx xxxx FPSLCT select register FFFA56 RW xxxx xxxx xxxx xxxx reserved FFFA58 RW xxxx xxxx xxxx xxxx FPIADR instruction address high FFFA5A RW xxxx xxxx xxxx xxxx FPIADR instruction address low FFFA5C RW xxxx xxxx xxxx xxxx FPOADR operand address high FFFA5E RW xxxx xxxx xxxx xxxx FPOADR operand address low Table M20: ACIA Registers FFFC00 RW xxxx xxxx ---- ---- Keyboard ACIA control FFFC02 RW xxxx xxxx ---- ---- Keyboard ACIA data FFFC04 RW xxxx xxxx ---- ---- MIDI ACIA control FFFC06 RW xxxx xxxx ---- ---- MIDI ACIA data Table M21: Mega ST Real-Time Clock Registers FFFC20 RW ---- ---- xxxx xxxx Bank 0: seconds (ones 0-9) Bank 1: clock output frequency 000 Open-collector CLKOUT 001 16,384 Hz 010 1,024 Hz 011 128 Hz 100 16 Hz 101 1 Hz 110 1/60 Hz 111 Open-collector CLKOUT FFFC22 RW ---- ---- xxxx xxxx Bank 0: seconds (tens 0-5) Bank 1: reset seconds FFFC24 RW ---- ---- xxxx xxxx Bank 0: minutes (ones 0-9) Bank 1: alarm minutes (ones 0-9) FFFC26 RW ---- ---- xxxx xxxx Bank 0: minutes (tens 0-5) Bank 1: alarm minutes (tens 0-5) FFFC28 RW ---- ---- xxxx xxxx Bank 0: hours (ones 0-9) Bank 1: alarm hours (ones 0-9) FFFC2A RW ---- ---- xxxx xxxx Bank 0: hours (tens 0-2 for 24 hour mode or 0-1 for 12 hour mode) bit 1 set = pm, bit 1 not set = am Bank 1: alarm hours as bank 0 FFFC2C RW ---- ---- xxxx xxxx Bank 0: days (0-6, Sunday = 0) Bank 1: alarm days as bank 0 FFFC2E RW ---- ---- xxxx xxxx Bank 0: date (ones 0-9) Bank 1: alarm date as bank 0 FFFC30 RW ---- ---- xxxx xxxx Bank 0: date (tens 0-3) Bank 1: alarm date as bank 0 FFFC32 RW ---- ---- xxxx xxxx Bank 0: months (ones 0-9) Bank 1: not used FFFC34 RW ---- ---- xxxx xxxx Bank 0: months (tens 0-1) Bank 1: bit 1 set = 24 hour mode FFFC36 RW ---- ---- xxxx xxxx Bank 0: years (ones 0-9) since 1980 Bank 1: leap year register (0-3) FFFC38 RW ---- ---- xxxx xxxx Bank 0: years (tens 0-9) Bank 1: not used FFFC3A RW ---- ---- ---- xx-x Mode register || |_ Bank select ||___ Alarm on/off |____ Clock start/stop FFFC3C RW ---- ---- xxxx xxxx Test register FFFC3E RW ---- ---- xxxx xxxx Reset register ||||_ Alarm reset |||__ Clock reset ||___ 16 Hz alarm pulse |____ 1 Hz alarm pulse Memory map - TT/Falcon An ST compatible image resides at address $00000000 with another at $FF000000. The first $800 (2,048) bytes of RAM ($00000008-$000007FF or $FF000008- $FF0007FF in the image) are reserved for the exception vectors and system variables. The first eight bytes of the ROM are shadowed at the start of RAM for the reset stack pointer and program counter. This area along with I/O space at $00FF8000 is protected for supervisor references only. Accessing supervisor protected areas while in the user state will result in a bus error. Writing to this area or any ROM location will also result in a bus error. The full ROM resides at the memory location $00E00000-$00EFFFFF with an image at $FFE00000-$FFEFFFFF. The following is a map of TT/Falcon memory as seen by the MC68030. Addresses are in hexadecimal. Table M22: General Memory Map - TT/Falcon Address Use 00000000 ROM Supervisor stack pointer 00000004 ROM Program counter 00000008 RAM Exception vectors 00000400 RAM System variables 00000800 RAM Main ST RAM start 009FFFFF RAM End of maximum physical ST RAM space 00A00000 Falcon030 RAM space, reserved on TT 00E00000 ROM Main system ROM space 00F00000 reserved TT I/O 00FA0000 ROM Cartridge ROM space 00FC0000 reserved 00FF8001 I/O Memory controller register 00FF8002 unassigned 00FF8006 I/O Falcon hardware configuration registers 00FF8008 unassigned 00FF8200 I/O Video controller registers 00FF82C4 unassigned 00FF8400 I/O TT palette registers 00FF8600 I/O ACSI DMA and FDC registers 00FF860E unassigned 00FF8700 I/O TT SCSI DMA control registers 00FF8716 unassigned 00FF8780 I/O TT SCSI controller registers 00FF8790 unassigned 00FF8800 I/O Programmable sound chip registers 00FF8804 unassigned 00FF8900 I/O DMA sound control registers 00FF8922 I/O TT MICROWIRE registers 00FF8926 unassigned 00FF8930 I/O Falcon DSP/DMA controller registers 00FF8944 unassigned 00FF8960 I/O TT real-time clock and NVRAM registers 00FF8964 unassigned 00FF8A00 I/O Falcon BLiTTER registers 00FF8A3E unassigned 00FF8C00 I/O TT SCC DMA control registers 00FF8C16 unassigned 00FF8C80 I/O SCC ports registers 00FF8C88 unassigned 00FF8E00 I/O TT VME system control unit (SCU) registers 00FF8E10 unassigned 00FF9200 I/O TT configuration switches 00FF9200 I/O Falcon extended joystick controllers registers 00FF9224 unassigned 00FF9800 I/O Falcon VIDEL palette registers 00FF9C00 unassigned 00FFA000 I/O TT main board peripheral expansion 00FFA200 I/O Falcon DSP host interface 00FFA208 unassigned 00FFFA00 I/O TT MFP-ST 68901 registers 00FFFA30 unassigned 00FFFA80 I/O TT MFP-2 68901 registers 00FFFAB0 unassigned 00FFFC00 I/O Keyboard and MIDI ACIA registers 00FFFC20 I/O unassigned 00FFFFFF End of I/O address space 01000000 RAM Start of TT fast RAM 01FFFFFF RAM End TT RAM space 02000000 reserved FE000000 VME TT VMEbus A24/D16 addressable area FEFF0000 VME TT VMEbus A16/D16 addressable area FF000000 ST shadow image of $0-$00FFFFFF FFFFFFFF End of address space Memory map I/O - TT/Falcon The TT/Falcon input/output space is at $00FF8000 to $00FFFFFF with an image at $FFFF8000. Accessing reserved I/O addresses will result in a bus error. The following is a map of TT I/O space where RW = Read/Write, RO = Read Only, WO = Write Only, 'x' marks a valid bit position in the byte or word and '-' marks an unused bit which is always assumed to have a value of zero. Each address shows a word or sixteen bits, the even (high) byte being on the left and the odd (low) byte on the right. Addresses are in hexadecimal. Table M23: Memory Controller Register FF8000 RW ---- ---- ---- xxxx As Table 4 Table M24: Falcon Hardware Configuration Register FF8006 RW xx-- ---- --x- -x-x Monitor type 00 | ST monochrome and compatible 01 | ST colour and compatible 10 | VGA and multisync monitors 11 | TV | Falcon clock control | 0 68030 8 MHz | 1 68030 16 MHz | 0 BLiTTER 8 MHz | 1 BLiTTER 16 MHz |_______ STE bus emulation (0 = on) Table M25: Video Controller Registers FF8200 RW ---- ---- xxxx xxxx Video base high FF8202 RW ---- ---- xxxx xxxx Video base middle FF8204 RO ---- ---- xxxx xxxx Video address counter high FF8206 RO ---- ---- xxxx xxxx Video address counter middle FF8208 RO ---- ---- xxxx xxxx Video address counter low FF820A RW ---- --xx Video sync mode ||___________ External/internal sync |____________ 50/60 Hz field rate FF820B WO 0000 0000 Reserved FF820C RW ---- ---- xxxx xxxx Video base low FF820E RW xxxx xxxx xxxx xxxx Line width (TT odd byte only) FF8210 RW xxxx xxxx xxxx xxxx Falcon line width FF8240 RW ---- 0321 0321 0321 ST palette colour 0 and border | | | |_ Inverted/normal monochrome | | |___ Blue | |________ Green |_____________ Red to FF825E RW ---- 0321 0321 0321 ST palette colour 15 FF8260 RW ---- --xx ---- ---- ST shift mode 00 320 x 200 x 4 planes 01 640 x 200 x 2 planes 10 640 x 400 x 1 plane 11 Reserved FF8262 RW x--x -xxx ---- xxxx TT shift mode | | ||||_ ST palette bank | |________________ Hyper mono mode |___________________ Sample and hold (smear) mode 000 320 x 200 x 4 planes 001 640 x 200 x 2 planes 010 640 x 400 x 1 plane 100 640 x 480 x 4 planes 110 1280 x 960 x 1 plane 111 320 x 480 x 8 planes FF8264 RW ---- ---- ---- xxxx Horizontal scroll FF8266 RW ---- -x-x -xxx ---- Falcon SPSHIFT control | | |||______ 256-colour mode | | ||_______ Internal/external vertical sync | | |________ Internal/external horizontal sync | |___________ True-colour mode |_____________ 2-colour mode FF8280 R0 xxxx xxxx xxxx xxxx Falcon horizontal hold counter FF8282 RW xxxx xxxx xxxx xxxx Falcon HHT synchro FF8284 RW xxxx xxxx xxxx xxxx Falcon HBB end of line FF8286 RW xxxx xxxx xxxx xxxx Falcon HBE start of line FF8288 RW xxxx xxxx xxxx xxxx Falcon HDB left overscan FF828A RW xxxx xxxx xxxx xxxx Falcon HDE right overscan FF828C RW xxxx xxxx xxxx xxxx Falcon HSS synchro FF828E RW xxxx xxxx xxxx xxxx Falcon HFS FF8290 RW xxxx xxxx xxxx xxxx Falcon HEE FF82A0 RO xxxx xxxx xxxx xxxx Falcon vertical frequency counter FF82A2 RW xxxx xxxx xxxx xxxx Falcon VFT synchro FF82A4 RW xxxx xxxx xxxx xxxx Falcon VBB end of image FF82A6 RW xxxx xxxx xxxx xxxx Falcon VBE start of image FF82A8 RW xxxx xxxx xxxx xxxx Falcon VDB top overscan FF82AA RW xxxx xxxx xxxx xxxx Falcon VDE bottom overscan FF82AC RW xxxx xxxx xxxx xxxx Falcon VSS synchro FF82C2 RW ---- ---- ---- -xxx Falcon VCO video control |||_ Line doubling ||__ Interlace mode |___ Halve pixel width FF8400 RW ---- 3210 3210 3210 TT palette colour 0 | | | |_ Inverted/normal monochrome | | |___ Blue | |________ Green |_____________ Red to FF85FE RW ---- 3210 3210 3210 TT palette colour 255 Table M26: ACSI DMA and FDC Registers FF8600 ---- ---- ---- ---- As Table M7 Table M27: TT SCSI DMA Control Registers FF8700 RW ---- ---- xxxx xxxx DMA pointer upper FF8702 RW ---- ---- xxxx xxxx DMA pointer upper-middle FF8704 RW ---- ---- xxxx xxxx DMA pointer lower-middle FF8706 RW ---- ---- xxxx xxxx DMA pointer lower FF8708 RW ---- ---- xxxx xxxx Byte count upper FF870A RW ---- ---- xxxx xxxx Byte count upper-middle FF870C RW ---- ---- xxxx xxxx Byte count lower-middle FF870E RW ---- ---- xxxx xxxx Byte count lower FF8710 RO xxxx xxxx xxxx xxxx Data residue register high FF8712 RO xxxx xxxx xxxx xxxx Data residue register low FF8714 RW ---- ---- xx-- --xx Control register || 0 DMA direction in from port || 1 DMA direction out to port || 0 DMA enable off || 1 DMA enable on ||________ Byte count zero read-only |_________ Bus error during DMA read-only Table M28: TT SCSI Controller Registers FF8780 RW ---- ---- xxxx xxxx Data FF8782 RW ---- ---- xxxx xxxx Initiator command FF8784 RW ---- ---- xxxx xxxx Mode FF8786 RW ---- ---- xxxx xxxx Target command FF8788 RW ---- ---- xxxx xxxx ID select/SCSI control FF878A RW ---- ---- xxxx xxxx DMA start/DMA status FF878C RW ---- ---- xxxx xxxx DMA target receive/input data FF878E RW ---- ---- xxxx xxxx DMA initiator receive/reset Table M29: Programmable Sound Chip Registers FF8800 RO xxxx xxxx ---- ---- PSG read data |||| |||| I/O port B ||||_||||___________ Parallel interface data FF8800 WO ---- xxxx ---- ---- PSG register select ||||___________ Register number 0000 Channel A fine tune 0001 Channel A coarse tune 0010 Channel B fine tune 0011 Channel B coarse tune 0100 Channel C fine tune 0101 Channel C coarse tune 0110 Noise generator control 0111 Mixer control - I/O enable 1000 Channel A amplitude 1001 Channel B amplitude 1010 Channel C amplitude 1011 Envelope period fine tune 1100 Envelope period coarse tune 1101 I/O port A (output only) 1111 I/O port B FF8802 WO xxxx xxxx ---- ---- PSG write data |||| |||| I/O port A |||| ||||___________ Floppy side 0/side 1 select |||| |||____________ Floppy drive 0 select |||| ||_____________ Falcon printer port SELECT |||| |______________ MFP-ST request to send ||||________________ MFP-ST data terminal ready |||_________________ Printer port STROBE ||__________________ Speaker disable = 0 |___________________ LAN select = 0 |||| |||| I/O port B ||||_||||___________ Parallel interface data Table M30: DMA Sound Control Registers FF8900 RW ---- xxxx x-xx --xx Sound DMA control |||| | || 00 Sound DMA disabled |||| | || 01 Sound DMA enabled |||| | || 11 Enabled, repeat frame forever |||| | || Falcon only: |||| | ||______ Record enable |||| | |_______ Repeat record |||| 0 Playback register select |||| 1 Record register select ||||___________ MFP-16 interrupt at playback end |||____________ MFP-16 interrupt at record end ||_____________ Timer A interrupt at playback end |______________ Timer A interrupt at record end FF8902 RW ---- ---- xxxx xxxx Frame base address high FF8904 RW ---- ---- xxxx xxxx Frame base address middle FF8906 RW ---- ---- xxxx xxxx Frame base address low FF8908 RW ---- ---- xxxx xxxx Frame address counter high FF890A RW ---- ---- xxxx xxxx Frame address counter middle FF890C RW ---- ---- xxxx xxxx Frame address counter low FF890E RW ---- ---- xxxx xxxx Frame end address high FF8910 RW ---- ---- xxxx xxxx Frame end address middle FF8912 RW ---- ---- xxxx xxxx Frame end address low FF8920 RW --xx --xx xx-- --xx Sound mode control 00 Falcon deactivate DMA transfer 00 TT 6,258 Hz sample rate 01 12,517 Hz sample rate 10 25,033 Hz sample rate 11 50,066 Hz sample rate 00 8-bit stereo mode 01 Falcon 16-bit stereo mode 10 8-bit mono mode 00 Falcon play 1 track 01 Falcon play 2 tracks 10 Falcon play 3 tracks 11 Falcon play 4 tracks 00 Falcon monitor track 0 01 Falcon monitor track 1 10 Falcon monitor track 2 11 Falcon monitor track 3 Table M31: TT MICROWIRE Registers FF8922 RW xxxx xxxx xxxx xxxx As Table M10 Table M32: Falcon DSP/DMA Controller Registers FF8930 RW --x- -xxx xxxx xxxx DMA crossbar output select | | | | DMA output: | | | |_ Handshake enable = 0 | | |00 25.175 MHz clock | | |01 External clock | | |10 32 MHz clock | | |____ DSP/DMA handshaking DMA in = 0 | | DSP output: | |______ Handshake enable = 0 | 00 25.175 MHz clock | 01 External clock | 10 32 MHz clock | 0 DSP tristate | 1 DSP connected to matrix | External input: |___________ Handshake enable = 0 00 25.175 MHz clock 01 External clock 10 32 MHz clock ADC input: 0 Internal 25,175 MHz clock 1 External clock FF8932 RW -xx- -xxx xxxx xxxx DMA crossbar input select | | | | DMA input: | | | |_ Handshake enable = 0 | | |00 DMA output | | |01 DSP output | | |10 External input | | |11 ADC input | | |____ DSP/DMA handshaking DSP out = 0 | | DSP input: | |______ Handshake enable = 0 | 00 DMA output | 01 DSP output | 10 External input | 11 ADC input | 0 DSP tristate | 1 DSP connected to matrix | External output: |___________ Handshake enable = 0 00 DMA output 01 DSP output 10 External input 11 ADC input DAC output: 00 DMA output 01 DSP output 10 External input 11 ADC input FF8934 RW ---- xxxx Frequency divider external sync ||||___________ 0-15 0 = STE compatible mode FF8935 RW ---- xxxx Frequency divider internal sync 0000 STE compatible mode 0001 CLK50K 49,170 Hz 0010 CLK33K 32,780 Hz 0011 CLK25K 24,585 Hz 0100 CLK20K 19,668 Hz 0101 CLK16K 16,390 Hz 0110 CLK14K 14,049 Hz (CODEC invalid) 0111 CLK12K 12,292 Hz 1000 CLK11K 10,927 Hz (CODEC invalid) 1001 CLK10K 9,834 Hz 1010 CLK09K 8,940 Hz (CODEC invalid) 1011 CLK08K 8,195 Hz 1100 CLK07K 7,565 Hz (CODEC invalid) 1101 CLK07K 7,024 Hz (CODEC invalid) 1110 CLK06K 6,556 Hz (CODEC invalid) 1111 CLK06K 6,146 Hz (CODEC invalid) FF8936 RW ---- --xx Record tracks select 00 Record 1 track 01 Record 2 tracks 10 Record 3 tracks 11 Record 4 tracks FF8937 RW ---- --xx CODEC input source ||_ ADC/DAC input = 1 |__ Multiplexer input = 1 FF8938 RW ---- --xx CODEC ADC input 0 Right microphone channel 1 Right PSG channel 0 Left microphone channel 1 Left PSG channel FF8939 RW xxxx xxxx Channel input amplifier gain |||| |||| (steps of +1.5 dB) |||| ||||_ Right channel 0-15 ||||______ Left channel 0-15 FF893A RW ---- xxxx xxxx ---- Channel output amp attenuation |||| |||| (steps of -1.5 dB) |||| ||||______ Right channel 0-15 ||||___________ Left channel 0-15 FF893C RW ---- --xx ---- ---- CODEC status ||___________ Right channel overflow |____________ Left channel overflow FF8940 RW ---- ---- ---- -xxx GPIO data direction 0 Read data from GP0 1 Write data to GP0 0 Read data from GP1 1 Write data to GP1 0 Read data from GP2 1 Write data to GP2 FF8942 RW ---- ---- ---- -xxx GPIO data pins |||_ GP0 ||__ GP1 |___ GP2 Table M33: TT Real-Time Clock and NVRAM Registers FF8960 RW ---- ---- xxxx xxxx As Table M11 Table M34: Falcon BLiTTER Registers FF8A00 RW xxxx xxxx xxxx xxxx As Table M12 Table M35: TT SCC DMA Control Registers FF8C00 RW ---- ---- xxxx xxxx DMA pointer upper FF8C02 RW ---- ---- xxxx xxxx DMA pointer upper-middle FF8C04 RW ---- ---- xxxx xxxx DMA pointer lower-middle FF8C06 RW ---- ---- xxxx xxxx DMA pointer lower FF8C08 RW ---- ---- xxxx xxxx Byte count upper FF8C0A RW ---- ---- xxxx xxxx Byte count upper-middle FF8C0C RW ---- ---- xxxx xxxx Byte count lower-middle FF8C0E RW ---- ---- xxxx xxxx Byte count lower FF8C10 RO xxxx xxxx xxxx xxxx Data residue register high FF8C12 RO xxxx xxxx xxxx xxxx Data residue register low FF8C14 RW ---- ---- xx-- --xx Control register || 0 DMA direction in from port || 1 DMA direction out to port || 0 DMA enable off || 1 DMA enable on ||________ Byte count zero read-only |_________ Bus error during DMA read-only Table M36: SCC Ports FF8C80 RW ---- ---- xxxx xxxx As Table 12 Table M37: TT VME System Control Unit (SCU) Registers FF8E00 RW ---- ---- xxxx xxx- As Table 14 Table M38: TT Configuration Switches FF9200 RW xxxx xxxx ---- ---- Table M39: Falcon Game Controllers Registers FF9200 RW ---- xxxx ---- ---- As Table M17 Table M40: Falcon VIDEL Palette Registers FF9800 RW 5432 10-- 5432 10-- Palette colour 0 |||| || ||||_||___ Green 0-63 ||||_||_____________ Red 0-63 FF9802 RW ---- ---- 5432 10-- Blue 0-63 to FF9BFC RW 5432 10-- 5432 10-- Palette colour 255 |||| || ||||_||___ Green 0-63 ||||_||_____________ Red 0-63 FF9BFE RW ---- ---- 5432 10-- Blue 0-63 Table M41: Falcon DSP Host Interface Registers FFA200 RW xxxx x-xx Host interrupt control | | | Host mode data transfers | | | Interrupt mode: | | | 00 No interrupts (polling) | | | 01 RXDF request (interrupt) | | | 10 TXDE request (interrupt) | | | 11 RXDF and TXDE request (interrupts) | | | DMA mode: | | | 00 No DMA | | | 01 DSP to host request (RX) | | | 10 Host to DSP request (TX) | | | 11 Undefined (illegal) | | |______________ Host flag 0 | |________________ Host flag 1 |00 Interrupt mode (DMA off) |01 24-bit DMA mode |10 16-bit DMA mode |11 8-bit DMA mode |___________________ INIT bit FFA201 RW x--x xxxx Command vector | |_||||_ Host vector 0-31 |_________ Handshake FFA202 RW xx-x xxxx Host interrupt status register ISR || | ||||___________ ISR receive data full RXDF || | |||____________ ISR transmit data empty TXDE || | ||_____________ ISR transmitter ready TRDY || | |______________ Host flag 2 || |________________ Host flag 3 ||__________________ ISR DMA status |___________________ ISR host request FFA203 RW xxxx xxxx Interrupt vector register FFA204 RW xxxx xxxx DSP word high FFA206 RW xxxx xxxx xxxx xxxx DSP word middle and low Table M42: TT MFP-ST 68901 Registers FFFA00 RW ---- ---- xxxx xxxx As Table M18 MFP is present on a Falcon but not used for serial communications Table M43: TT MFP-2 68901 Registers FFFA80 RW ---- ---- xxxx xxxx General purpose I/O GPIP FFFA82 RW ---- ---- xxxx -xxx Active edge AER |||| |||_ Centronics busy |||| ||__ RS-232 carrier detect |||| |___ RS-232 clear to send ||||______ Keyboard/MIDI interrupt |||_______ FDC/HDC interrupt ||________ RS-232 ring indicator |_________ Monochrome monitor detect FFFA84 RW ---- ---- xxxx xxxx Data direction DDR FFFA86 RW ---- ---- xxxx xxxx Interrupt enable A IERA |||| ||||_ Timer B (HBlank counter) |||| |||__ Sender error |||| ||___ Sender buffer empty |||| |____ Receive buffer empty ||||______ Receive buffer full |||_______ Timer A (DMA sound counter) ||________ RS-232 ring indicator |_________ Monochrome monitor detect FFFA88 RW ---- ---- xxxx xxxx Interrupt enable B IERB |||| ||||_ Centronics busy |||| |||__ RS-232 carrier detect |||| ||___ RS-232 clear to send |||| |____ BitBLT complete ||||______ Timer D (baud rate generator) |||_______ Timer C (200 Hz system clock) ||________ Keyboard/MIDI interrupt |_________ FDC/HDC interrupt FFFA8A RW ---- ---- xxxx xxxx Interrupt pending A IPRA mapping as for IERA FFFA8C RW ---- ---- xxxx xxxx Interrupt pending B IPRB mapping as for IERB FFFA8E RW ---- ---- xxxx xxxx Interrupt in-service A ISRA mapping as for IERA FFFA90 RW ---- ---- xxxx xxxx Interrupt in-service B ISRB mapping as for IERB FFFA92 RW ---- ---- xxxx xxxx Interrupt mask A IMRA mapping as for IERA FFFA94 RW ---- ---- xxxx xxxx Interrupt mask B IMRB mapping as for IERB FFFA96 RW ---- ---- ---- x--- Vector VR 0 Automatic end-of-interrupt 1 Software end-of-interrupt FFFA98 RW ---- ---- ---- xxxx Timer A control TACR 0000 Timer stop 0001 Delay mode, divide by 4 0010 Delay mode, divide by 10 0011 Delay mode, divide by 16 0100 Delay mode, divide by 50 0101 Delay mode, divide by 64 0110 Delay mode, divide by 100 0111 Delay mode, divide by 200 1000 Event count mode 1001 Pulse extension mode 1001 Pulse extension mode, divide by 4 1010 Pulse extension mode, divide by 10 1011 Pulse extension mode, divide by 16 1100 Pulse extension mode, divide by 50 1101 Pulse extension mode, divide by 64 1110 Pulse extension mode, divide by 100 1111 Pulse extension mode, divide by 200 FFFA9A RW ---- ---- ---- xxxx Timer B control TBCR mapping as for TACR FFFA9C RW ---- ---- -xxx -xxx Timers C and D control TCDCR 000 Timer C stop 001 Timer C delay mode, divide by 4 010 Timer C delay mode, divide by 10 011 Timer C delay mode, divide by 16 100 Timer C delay mode, divide by 50 101 Timer C delay mode, divide by 64 110 Timer C delay mode, divide by 100 111 Timer C delay mode, divide by 200 000 Timer D stop 001 Timer D delay mode, divide by 4 010 Timer D delay mode, divide by 10 011 Timer D delay mode, divide by 16 100 Timer D delay mode, divide by 50 101 Timer D delay mode, divide by 64 110 Timer D delay mode, divide by 100 111 Timer D delay mode, divide by 200 FFFA9E RW ---- ---- xxxx xxxx Timer A data TADR FFFAA0 RW ---- ---- xxxx xxxx Timer B data TBDR FFFAA2 RW ---- ---- xxxx xxxx Timer C data TCDR FFFAA4 RW ---- ---- xxxx xxxx Timer D data TDDR FFFAA6 RW ---- ---- xxxx xxxx Sync character SCR FFFAA8 RW ---- ---- xxxx xxx- USART control UCR |||| |||__ Parity |||| ||___ Even/odd parity |||0 0 Synchronous |||0 1 1 stop, 1 start bits |||1 0 1 stop, 1.5 start bits |||1 1 1 stop, 2 start bits |00 8 bits |01 7 bits |10 6 bits |11 5 bits |_________ Clock divide by 16 FFFAAA RW ---- ---- xxxx xxxx Receiver status RSR |||| ||||_ Receiver enable |||| |||__ Synchronous strip enable |||| ||___ Match/character in progress |||| |____ Search/break detect ||||______ Frame error |||_______ Parity error ||________ Overrun error |_________ Buffer full FFFAAC RW ---- ---- xxxx xxxx Transmitter status TSR |||| ||||_ Transmitter enable |||| |||__ Low bit |||| ||___ High bit |||| |____ Break ||||______ End of transmission |||_______ Auto-turnaround ||________ Underrun error |_________ Buffer empty FFFAAE RW ---- ---- xxxx xxxx USART data UDR Table M44: ACIA Registers FFFC00 RW xxxx xxxx ---- ---- As Table M20 Memory protection The procedures used to prevent the corruption of data in one memory block from the processing of data in another memory block. In multitasking situations, each task or program occupies and uses memory that needs to be isolated from other memory blocks so that one program doesn't overwrite another's data or when one program crashes, that corruption doesn't affect the other programs. On-board memory protection is a feature of the MC68030 thus making MultiTOS safer to run and more successful on a TT than on the ST range. Memory Usage Parameter Block - MUPB The Operating System Header offset $14 points to the MUPB which has the structure: typedef struct { long gem_magic; /* Value of $87654321 if GEM present */ long gem_end; /* End address of OS RAM usage */ long gem_entry; /* Start address of GEM */ } MUPB; GEM is only executed at start-up if gem_magic is $87654321. Menu In an interactive system, a list of items (sometimes hierarchical) with identifiers by which they may be selected by the keyboard or mouse. Menu bar A GEM application's primary menu consisting of a horizontal list on the screen top row from which vertical lists of items can be pulled for selection. The first item on the left should be the program's name with access to accessories. In MultiTOS this also provides access to the other active programs. The second menu should always be the "File" menu and the third "Edit", followed by an "Options" menu if applicable and any other application- specific menus. The last menu item should be "Help". Merge To combine two sets of data to form a single set, sometimes by re-sorting the order of the items. Message In communications, a unit of data with addressing and control characters transmitted between computers. Also, a report from the computer to a user. Message channel The forward channel. Metafile A standard GEM vector graphics file format with a .GEM extender as produced by programs such as Easydraw. See GEM metafile. MetaDOS The Atari CD-ROM driver program which Atari released as freeware. Metering pulses Counted pulses sent at intervals during a telephone call to determine the call's length and charge. MFLOPS Mega FLoating point OPerations per Second. A measurement of the speed of operation of a FPU in millions of operations per second. MFM Modified Frequency Modulation. An outdated method of encoding data onto a magnetizable surface, such as floppies and some hard disks, that is similar to FM except that fewer flux transitions are required to encode a given amount of data. It provides around twice the data density of the FM method (single density) and is often referred to as double density recording. This method was used on the original Shugart ST506 hard disks but the RLL method is capable of even greater data density and is more common. MFP 68901 Multi-Function Peripheral 68901. A Motorola 48-pin DIL or 52-pin PLCC packaged chip found in the whole Atari range providing an 8-bit parallel port with each pin independently programmable, a serial interface, four universal system timers and sixteen interrupt sources and includes monochrome monitor detect and parallel printer port busy signals handling. It operates at a speed of 4 MHz on the ST and has its own 2.4567 MHz crystal for the serial port. One of its main roles is to control RS-232C I/O on the ST. On the Mega STE and TT there are two MFP controllers, one being compatible with that on the ST and designated MFP-ST. The second (MFP-2) provides another low-speed serial port and more I/O and interrupt pins. Transfer rates of up to 19.2 Kbps can be provided on these ports. Both are 9-pin DB connectors compatible with IBM PC AT. See RS-232C, RS-232 port, Exception vectors. MHS Message Handling Service. The CCITT name for e-mail. MICR Magnetic Ink Character Recognition. A technique of reading characters printed in magnetic ink and generating their bit-patterns for computer input. Commonly used for sorting bank cheques. Micro A microprocessor or usually a microcomputer. Micro - æ Prefix meaning one millionth (10^-6). Also meaning 'very small'. Microcode The micro-instructions held in the ROM of a CPU and output to logic gates as a step in executing an instruction. It is this set of microcode that determines what a CPU can do. Microcomputer Small personal computer with a microprocessor and memory. Typically, a desktop unit with floppy and small hard disk storage and a monitor. The microprocessor may be an 8, 16 or 32-bit device typically from the Intel 80x86 series (or compatible devices) or the Motorola 680x0 series. RAM may be anything from 1 K to 32 Mb or more, although 1 Mb to 4 Mb is usual and the most common operating system is MS-DOS. Microfiche Photographic film of standard size with a number of frames of microfilm arranged in a grid pattern. Microfilm High resolution photographic film suitable for recording images with large reductions, typically 42 times. It is mainly used for archival purposes. Microfloppy A term originally used to describe 3.5 inch floppy disks. Microprocessor - MPU A single integrated circuit that performs instruction execution and monitor and control functions for an intelligent device such as a computer or modem. It is the CPU of a microcomputer. It typically consists of a ROM to hold the microcode, an instruction register to hold the currently executing instruction, a program counter register to hold the address of the next instruction, an arithmetic and logic unit (ALU), registers for holding addresses, input and output data, small amount of RAM, integral clocks etc. MICROWIRE The MICROWIRE bus interface was introduced with the STE and provided the interface to the National LMC1992 Volume/Tone Control chip and was intended to be used to interface with other devices. The MICROWIRE bus is a low-level three-wire serial connection and protocol designed to allow multiple devices to be individually addressed by the controller. Two 16-bit read/write registers are provided on the STE, one for the data and the other a mask. Any one-bit in the mask register indicates that the corresponding bit in the data register is valid. Data transmission starts as soon as the data register has been written to, so that the mask register has to be written to first. The devices on the MICROWIRE bus are addressed by a 2-bit address field with the Volume/Tone controller being device %10 binary. The MICROWIRE interface was dropped on the Falcon030. MIDI Musical Instrument Digital Interface. A high-speed multichannel, serial, data link with up to sixteen devices usually musical instruments or controllers. The ST-Falcon range have MIDI IN and MIDI OUT ports and the operating system supports them with appropriate functions. From the early days of the ST's existence these ports and the introduction of sequencing and score writing software made it a popular choice with musicians and recording studios, and has established a strong dominant niche in this area for the ST. The MIDI standard is based on the current loop principle which is not so susceptible to noise, especially with cheap unscreened cable. The transfer rate is 31,250 bps and data is sent as a serial stream of 8-bit words preceded by a 1-bit start bit and a 1-bit stop bit. All MIDI devices are connected together in a chain, the output MIDI socket of one connected to the input socket of the next. This allows all the devices to communicate with each other and the controlling computer, such as the ST. As sixteen devices or channels can be connected to this bus, each data packet is preceded with the channel number of the device it is meant for. Each MIDI IN and OUT port on a ST is coupled to an opto-isolator which prevents any current directly entering the computer from the port. It also converts the current loop signals into the normal TTL levels for the ST. The current loop travels out on pin 4 of the MIDI OUT connector and returns at pin 5 when a device is connected. MIDI IN is reversed where data is received on pin 4 and the loop return is on pin 5. No other pins are connected on MIDI IN but on the MIDI OUT connector pins 1 and 3 implement the MIDI THRU function. Milli - m Prefix meaning one thousandth (10^-3). MIME Multi-purpose Internet Mail Extensions. A relatively new method in transferring binary files by e-mail, usually over the Internet. MIME compliant programs can convert any attached binary file to its original state, whether sound, an image or another program. See UUENCODE. Mini Not as small as micro. Also a minicomputer. Minicomputer A computer between a mainframe and microcomputer in size, capability and cost, the latter being the main differentiating feature. The difference in the raw processing power between minis and micros is increasingly becoming negligible although the former do still have a greater networking and multitasking capability. MINIWIN MINIWIN.APP is a small program released with MultiTOS that enables .TOS and .TTP programs to be run within a GEM window environment so that they do not take over the whole screen, allowing access to other programs and processes. The window becomes a virtual screen and can be moved and re-sized which will hide some of the program's output. Different fonts and sizes can be installed and the Atari Clipboard is available for cutting and pasting output into other programs. MINIWIN is a simple program and lacks some of the versatility and intelligence of MW. See MW, MultiTOS. MiNT MiNT Is Not TOS. A freeware operating system written by Canadian Eric Smith for the Atari ST providing some multitasking capabilities to TOS. It allows one GEM program and several TOS programs to multitask on a MC68000 processor and uses many methods, techniques and utilities taken from the UNIX operating system. It also adds interprocess communications features, very simple multi- user capabilities and a flexible file system interface that permits loadable file systems and device drivers. In 1991 Atari obtained a licence from Eric Smith to modify it adding memory protection and included the MiNT system into the kernel of MultiTOS so that MiNT now stands for 'MiNT Is Now TOS'. See MultiTOS for a fuller discussion. MINT.CNF An ASCII text configuration file for MultiTOS loaded at boot-up and used to set some MiNT variables and to execute commands. The variable names must be in upper case and no spaces are allowed between them, the '=' character and the following values. Table M45: MiNT Variables in the MINT.CNF File Variable Meaning INIT= Execute the AES/GEM file e.g. INIT=C:\MULTITOS\GEM.SYS GEM= Execute the AES/GEM file via exec_os vector e.g. GEM=C:\MULTITOS\GEM.PRG CON= Redirect console input and output to named file e.g. CON=U:\DEV\SERIAL1 PRN= Redirect printer output to named file e.g. PRN=I:\OUTPUT.LST DEBUG_LEVEL= Set MiNT debugging level (0-4, 0 = default) e.g. DEBUG_LEVEL=1 DEBUG_DEVNO= Set BIOS device number to receive debug messages e.g. DEBUG_DEVNO=1 SLICES= Set number of 20 ms times slices given to process (default is 2) e.g. SLICES=3 MAXMEM= Set maximum memory a process can grab in kilobytes (default is unlimited) e.g. MAXMEM=2048 BIOSBUF= Enable/disable BIOS optimizations e.g. BIOSBUF=Y The command names must be in lower case with a single space between the command and the following argument. Table M46: Commands recognized in the MINT.CNF File Command Meaning echo Display a string on the screen e.g. echo MiNT is configured cd Change the GEMDOS default directory e.g. cd c:\multitos ren Rename a file e.g. ren c:\cpx\env.cpx c:\cpx\env.cpz exec Execute a program e.g. exec c:\utils\uis_iii.prg setenv set up an environment variable e.g. setenv clipbrd=c:\clipbrd alias Create an alias drive e.g. alias z: u:\c\mint sln Create a symbolic link on drive U: e.g. sln c:\mint\bin u:\bin The setenv can be set either in the MINT.CNF or the GEM.CNF file. They are usually best set in the latter. See MultiTOS, MiNT, GEM.CNF MiNT errors These error codes are the same as those for the GEMDOS errors. Mintshel Mintshel is a simple CLI shell that can be used as MultiTOS's and MiNT's initial shell (i.e. on the INIT= line of MINT.CNF in earlier versions of MultiTOS), and/or as the shell that runs in MW windows (specified on the SHELL line in MW.CNF). This shell is useful mainly because it knows all about MiNT, and supplies redirection, job control (backgrounding) and true pipes. MiNT signals Signals are messages sent to a process that are interpreted and acted upon accordingly. They normally stop the execution of that program. Table M47: MiNT Signals Name No Meaning SIGNULL 0 Dead signal, no effect SIGHUP 1 Hang-up signal, terminal no longer valid SIGINT 2 Interrupted by [Cntl-C] SIGQUIT 3 Quit signal [Cntl-\] SIGILL 4 Illegal instruction exception SIGTRAP 5 Single-step trace mode trap SIGABRT 6 Abort signal, lethal internal error SIGPRIV 7 Privilege violation exception SIGFPE 8 Divide by zero exception SIGKILL 9 Kill process, cannot be ignored SIGBUS 10 Bus error exception SIGSEG 11 Address error exception SIGSYS 12 Bad or out-of-range argument to a system call SIGPIPE 13 Broken pipe, has no readers SIGALRM 14 Alarm clock triggered SIGTERM 15 Software termination request SIGURG 16 Urgent condition on I/O channel SIGSTOP 17 Stop signal, not from terminal SIGTSTP 18 Stop signal, from terminal by [Cntl-Z] SIGCONT 19 Continue stopped process SIGCHLD 20 Child stopped or exited SIGTTIN 21 Read by background process SIGTTOU 22 Write by background process SIGIO 23 I/O possible on a descriptor SIGXCPU 24 CPU time exhausted SIGXFSZ 25 File size limited exceeded SIGVTALRM 26 Virtual timer alarm SIGPROF 27 Profiling timer expired SIGWINCH 28 Window size changed SIGUSR1 29 User signal 1 SIGUSR2 30 User signal 2 Handler returns: SIG_DFL 0 Default signal action SIG_IGN 1 Ignore signal action SIG_ERR -1 Error return MIPS Million Instructions Per Second. A measurement of the processing power of a CPU although in practice it, like most benchmark figures, has little useful meaning. MIT Massachusetts Institute of Technology. A leading centre for technology and scientific research. Mixed number A number that is not an integer, such as 7.5. MMU Memory Management Unit. A semiconductor device that manages a CPU's memory requests which may be a separate chip or part of that CPU. Also, an Atari custom chip usually in a square 68-pin PLCC package (it is sometimes surface mounted) providing and controlling the interface between the RAM and other chips including the CPU, SHIFTER and DMA. It specifically handles the memory addressing for them coupling the multiplexed address bus of the RAM with the processor's bus. It also looks after DRAM memory refreshing and helps to produce the video signal with the SHIFTER. A 4 MHz and 8 MHz signal is provided from a 16 MHz clock signal, the latter required for the MC68000. There are several different types for the ST, the 'IMP' one being less stable and cannot handle unequal banks of memory. The '-38' MMU is the better version. On the ST, although the 68000 can address 16 Mb of memory, the design of the MMU restricts this to 4 Mb maximum. Other computers have different MMUs because of the differing memory configurations and requirements of them. The STE MMU a the memory bank allocation problem, which means that 2.5 Mb is impossible. The TT has a MMU for the installed ST RAM on the motherboard and extra ones present on the memory upgrade boards for extra ST RAM or TT RAM. Mnemonic Something that aids human memory such as the 'Richard Of York Gave Battle In Vain' chant to remember the colours of the rainbow. Also, applied to elements of a programming language, especially assembly code e.g. RTS for Return from Subroutine. MNP Microcom Networking Protocol. A standard data error-correcting system found in most modern modems (MNP 2, 3 and 4), except that the MNP 5 protocol is concerned with data compression. These were de facto standards for a few years but for all intents and purposes are replaced by the CCITT V.42 standard for error correction and V.42bis for data compression both of which give superior performance. Modal An operating condition that consists of modes. Mode An operating condition that is one of two or more such conditions, i.e. command mode and edit mode. A mode exists if at any time you can't get to all of the capabilities of a program without taking some intermediate step. GUI/WIMP applications tend to be amodal (in theory) which is one of their main advantages. See Amodal. Modem MODulator/DEModulator. A data communications device that modulates and demodulates a carrier wave in order to represent data on a telephone line. When transmitting, it receives data as direct current pulses from a computer or terminal, generates a carrier wave and modulates it to represent data. When receiving, it converts modulations to direct current pulses and passes them to the computer. Most modems also have facilities for varying the speed of transmission, circuit testing, error corrections and data compression. Moderator A person who regulates a conference, echo or newsgroup for content and style. Modify To change an item of hardware or software to improve performance or reliability. Modular Consisting of modules. Modular programming A programming technique in which the problem, and hence the program, is broken down into logical subdivisions each being coded and tested separately. Modulation The process of changing a carrier wave in order for it to carry significant data. Also, a way of representing data on a magnetizable surface. Modulator A device that produces a RF (Radio Frequency) television signal thus allowing the use of a TV as a computer's VDU. On the ST, a Motorola 1377P chip is used to convert the SHIFTER's RGB signals and the GLUE's sync signals to a composite video output in PAL or NTSC format. This signal is fed to the monitor socket where it can be used to drive a monitor. The signal is also fed to a UHF modulator which converts it into a UHF TV signal which is only really acceptable at low resolution, the quality being very poor when compared to a computer monitor. Module A part of a whole that is capable of separate consideration or use, such as a sequence of instructions written as a unit in a modular program. Modula-2 A high-level language with a modular structure developed from and a successor to Pascal. Monadic Consisting of, or performed on a single item, such as the logic operator NOT and the monadic expression NOT 2 or -3. Monitor To check an operation as it is being performed and often applied to a device or program carrying out this function, especially low-level debuggers. Also, applied to operating system routines that perform physical operations, such as inputs and outputs. Also, a CRT visual display device. Monochrome A display or printed material consisting of one colour on another, usually black on a white background or its reverse. Monospaced font A typeface consisting of characters of equal width, such as the TOS system fonts and the Courier printer font. See Proportional. Most significant bit - MSB In a bit-group, the leftmost and highest weighted bit and transmitted last. Most significant byte - MSB In a group of bytes (a word or long word), the byte that is at the farthest left position having the greatest weight. Most significant digit - MSD The leftmost and highest weighted digit in a number in a positional representation system, such as the 1 in 125. Motherboard The main printed circuit board to which other removable boards connect. Motorola The US company that produces, among others, the MC680x0 series of processors. Mouse A device with one to three buttons used for controlling a special cursor (normally an arrow pointer) for the manipulation of screen items in GUI/WIMP environments. The mouse is held under the palm of the hand and moved over a flat surface, the mouse cursor making corresponding movements on the screen. The buttons can be used to click on certain graphic or menu items to initiate an action. The Atari mouse has the minimum performance characteristics of a resolution of 100 dpi, a maximum velocity of ten inches per second and a maximum pulse phase error of 50%. It is an optomechanical device consisting of four infra-red photocoupler light beams, two encoder wheels (discs with radial slots in them) and a drive mechanism consisting of two metal rollers attached to the wheels. As the mouse is moved so is the rubber-coated ball inside which moves against the two rollers which in turn move the two encoder wheels whose drive axes are at an angle of 90ø to each other. These alternately interrupt the infra-red light beams and the pulses from these are sent to the HD6301 informing it about the absolute path travelled on each axis. This scales the data and sends it to the processor to move the mouse pointer on the screen. To work out the direction of movement another two light beams are used on each encoder wheel. They are arranged so that they are not shielded by the wheel at the same time but one shortly after another. The direction is determined by which of the two light beams on each wheel is interrupted first. The left mouse button switch tends to wear with use and can be rejuvenated by placing one or two slips of paper between the switch and the long button extension or by swapping over the right and left microswitches. Mouse accelerator The Atari mouse normally has a resolution of 128 dpi, that is it has to be moved five inches to move the mouse pointer across a ST high resolution screen. This is normally too low, and a more responsive resolution is about 200-300 dpi. Many programs are available which increase the movement of the mouse pointer on the screen and some will also provide another acceleration effect, where the amount of movement on the screen is proportional to the speed of movement of the mouse. A fast movement of the mouse moves the pointer a long way, whilst careful individual pixel control can still be achieved by moving slowly. Mouse mat, mouse pad A mat on which to move the mouse providing a smoother action than a desk or table top. Mouse pointer The small arrow pointer that moves on the screen of a GUI/WIMP program when the mouse is moved. Normally an arrow, the shape may change depending on the activity of the computer. A pointing finger hand, a grabbing flat hand, a busy bee, a vertical bar text cursor and thin, thick and outline cross hairs are available for programmers. Selective use of these icons by a programmer can inform the user as to the program's current operational state. See Bee icon. Move To read data from one location and to write it to another and then delete the original copy so that only one remains. See Copy. Move bar The shaded top border of GEM windows which allows the window to be dragged to another position on screen with the mouse. MPEG Moving Picture Expert Group. An organization set up to decide the technical standard to be adopted for full-screen, full-motion video (FSFMV) on CD-ROM. MPU Micro-Processor Unit. MSB Most Significant Bit or Most Significant Byte. MS-DOS MicroSoft Disk Operating System. The standard operating system for IBM PCs and compatibles based on the original PC-DOS. Version 3.3 is the earliest usable version, version 4 is seriously flawed and versions 5 and 6 have significant improvements. TOS works in a very similar way to MS-DOS sharing many of the same function calls even to the extent of having the same number. The two operating systems are, however, totally incompatible with each other although MS-DOS formatted floppy disks can be read on TOS machines and the TOS format function on TOS 1.4 and above is capable of producing disks readable on MS- DOS-based computers. MSI Medium Scale Integration. MTBE Mean Time Between Errors. The average time that a computer operates without a system software error. MTBF Mean Time Between Failures. An indication of reliability of equipment being the average time it operates without a failure. MUG Multi-User Game. A game capable of being played by many people at once and continually over a period of time and which is accessed by connecting to a BBS or other service via a modem or network. Multi Prefix meaning 'more than one'. Multi-access Synonymous with multi-user. MULTICS MULTiplexed Information and Computing System. A 1960s operating system developed to allow several users access to one mainframe computer at the same time with the computer sharing its time between them. A slimmed down and much developed version of this became UNIX. Multimedia Although the term means different things to different people and at different times, loosely it is a hypertext document containing many different types of data - text, images, audio and video information. Multimedia is intended to be very user-interactive and user-friendly. Multimeter A meter that can measure several different electrical values. Multipart stationery Continuous stationery with multiple sheets interleaved with carbon paper or of carbonless copy paper and used in an impact printer to form multiple copies. Multiplexing A method of using a single communications channel to carry multiple speech and/or data transmissions simultaneously. Multiplexor A device that performs multiplexing in a data communications system. Also, an integrated circuit in which multiple input circuits are selectively connected to a single output circuit, usually buffering all signals so that they all eventually pass through. Multiprocessor A computer system with two or more processors under control of a single operating system. The system may be carrying out parallel processing or may consist of a main computer with one or more specialized auxiliary computers. Multiprocessing The processing of a multiprocessor, where one or more computer programs or tasks are run simultaneously on one or more processors. The term implies parallel processing. Multiprogramming A method of computer operation in which two or more application programs are being executed simultaneously by the interleaved allocation of a single set of computer resources. Most systems are interrupt (event) driven. The time during which the instructions of a particular program are being processed is a time slice. The operating system may manage the programming by allocating different time slices to different programs depending on their priorities as set by the user or the program itself. Once each time slice is up, execution control is passed to another program and so on around all the executing programs. MultiTOS operates in this manner as does the multitasking TOS replacement MagiC. Multiscan monitor A CRT display monitor operating at any of many line and frame frequencies thereby being compatible with all the resolutions of a computer system, such as those on the ST and TT. Multisync monitor A trademark of NEC and a multiscan monitor. Multitasking The operation of simultaneously executing a main task and subtasks belonging to the same program that are either interleaved (by a single processor) or executed concurrently (by a multiprocessor). MultiTOS The pre-emptive multitasking TOS based on the freeware MiNT project and officially introduced on the Falcon030. It essentially provides a multiprogramming environment in protected mode on a MC68030 running GEM and TOS programs under the NewDesk Desktop or any other shell. MultiTOS uses a pre-emptive time slicing system, where each process executes for a small number of clock cycles, interrupted by MiNT which chooses the next process to run and then runs that for a given slice of processor time. Depending on whether processes are running, asleep or waiting, the length of this time slice may vary and the priority of a program can be altered thus increasing its speed of operation although to the detriment of the other processes, of course (see Multiprogramming). Of particular importance is that the system doesn't have to wait for permission from one application before switching to another task, meaning that, for instance, a word processor doesn't have to finish its spell checking first before the user can swap to another program. MultiTOS has expanded interprocess communication with drag and drop facilities, so that a file can be dropped onto the window of an open application or a system driver file and be handled appropriately. Many applications can be open at the same time, and visible on the Desktop, and switching between applications or processes can be achieved by selecting their entry from the "Desk" menu underneath the accessories, or by topping the window owned by the process. Active applications place their menu bar across the top of the screen, where having the title of the first menu item (normally "Desk") the name of the program is now a vital necessity. There are no limits (except those of memory and screen space) on the number of open windows. .TOS and .TTP programs can be run from within moveable and re-sizable windows, such as MINIWIN using small system fonts so that they don't take over the whole screen. They also work much faster and more cleanly like this. Depending on the application, some windows can be minimized using the Smaller icon so as not to clutter up the Desktop and background windows can be moved and manipulated easily. MultiTOS will also work on a MC68000 machine but without memory protection because the 68000 processor cannot provide those facilities. Memory protection means that a program cannot access and write over the memory belonging to another program or process, but it will not stop programs crashing the system altogether. The 68030 can catch these illegal memory accesses allowing MultiTOS to kill off the process and return its memory to the free memory pool. 68000-based systems suffer badly from this inadequacy. Because of its history, many of the utilities, tools and general feel of MultiTOS are very UNIX-like. UNIX is quickly adopting a system of representing everything in an operating system, including all processes, as a file making them easily accessible and allowing for simple piping and other interprogram communication. MultiTOS's pseudo drive U: (for Unified) is an example of this and contains 'files' that represent disk drives, devices, pipes and processes contained in 'directories'. These are not real files, but file access calls can be used to deal with them. In addition to creating a folder for each installed system drive or partition, MiNT also creates the following directories in the root of drive U: Table M48: MultiTOS U: drive folders \DEV Default and loaded devices \PIPE System pipes \PROC System processes \SHM Shared memory blocks The U:\DEV folder contains a list of the BIOS devices, such as the mouse, screen, RS-232 port, printer port, etc. A file could be sent to the modem, for instance, by dropping it on the U:\DEV\AUX file. Devices may be loaded at any time. The following devices are available by default in U:\DEV Table M49: MultiTOS Default Devices CENTR Centronics (parallel) printer port MODEM1 Modem serial port 1 MODEM2 Modem serial port 2 SERIAL1 Serial port 1 SERIAL2 Serial port 2 MIDI MIDI port KBD Intelligent keyboard controller PRN Printer device (usually the parallel port) AUX Auxiliary terminal (usually the RS-232 port) CON Current control terminal TTY Same as CON STDIN Current file handle 0 (standard input) STDOUT Current file handle 1 (standard output) STDERR Current file handle 2 (standard error) CONSOLE Physical console, the keyboard/screen MOUSE Mouse (system use only) NULL A null device (like UNIX's /DEV/NULL) AES_BIOS AES BIOS device (system use only) AES_MT AES multitasking device (system use only) Alternative device drivers can also be loaded, automatically if they have a .XDD file name extender and found in the root or \MULTITOS folder. Loadable file systems, such as POSIX and ISO 9660 CD-ROM, are also automatically loaded if they have a .XFS extender and found in the same place. U:\PIPE contains files which are FIFO queues (e.g. pipes). All files created in U:\PIPE are temporary so that it is erased when the last program using a FIFO closes it. U:\PIPE is usually empty, but will contain items when running a window manager, print spooler or similar programs that use FIFOs or pseudo- TTYs for communication, like MINIWIN or MW. U:\PROC contains a list of processes. Listing U:\PROC gives information about currently executing processes, such as whether they're running, ready, or waiting, their process ID numbers and the amount of memory they've taken. The 'file name' is the name of the process with the process ID number as the extender. The 'file size' of a process file is the amount of memory that is allocated to it. The 'date/time stamp' reflects how much processor time it has consumed. The current state of a process is shown by the attribute bits of the 'file', most of which are not visible from the Desktop but can be used by programs. Table M50: Attribute Bits for Process 'Files' on U:\PROC Attribute Process state bit 0 Currently running 1 Ready to run 2 Waiting for an event 3 Waiting for I/O 4 Zombie (exited and not yet released) 5 Terminated and resident (TSR) 6 Stopped by a signal The 'zombie' state is for processes which have exited, but whose parents haven't yet learned their exit codes. Deleting a U:\PROC 'file' will send a SIGTERM signal to the corresponding process, which will usually result in that process being terminated. It is not possible to delete TSR or zombie processes. See MiNT signals. U:\SHM contains the shared memory blocks. With the availability of memory protection applications can share the same blocks of memory as though they were disk files. In this way, simultaneously running programs can share common sections of code or resource details. Other drives are accessible on drive U: as directories. U:\C is drive C: so the file C:\MULTITOS\SHOW.PRG is also visible as U:\C\MULTITOS\SHOW.PRG. MultiTOS supports Terminate and Stay Resident (TSR) programs and will continue to do so because there are so many of them. However, they are obsolete under a multitasking environment. Many simple ones, such as print spoolers, are designed to provide services in the background and should be rewritten as normal TOS programs. They can check the MiNT cookie to decide if to run as a TSR or as a TOS program. Other TSRs provide extended system services, such as access to unusual types of devices. MultiTOS provides facilities to make this extension easy with device drivers and loadable file systems. Device drivers, such as printer and serial port drivers go into globally accessible memory and MultiTOS makes it visible to GEMDOS and even the BIOS and takes care of read and write requests. Loadable file systems provide access to services by emulating a disk drive. This is useful for accessing drives that use a different format from TOS and MS-DOS, such as CD-ROMs and UNIX disk drives. The MiNT Extendable File System XFS driver supports standard CD-ROM, as well as CD-ROM/XA. In a multitasking environment, programs must not allocate large amounts of memory to themselves to the detriment of other programs which are running or to be run. One of the most dangerous system calls is Malloc(-1L) which supplies the size of the largest unallocated block of ST RAM memory in the system. This call isn't reliable because memory can be allocated or freed by another process between the time the system call is made and its value is used. A program should only allocate as much memory as is required by the task in hand and no more. If this Malloc() call fails then the program should try with a smaller block until it gets some memory or the Malloc() call fails entirely. In the future, MultiTOS may incorporate memory block paging or swapping (to and from disk, for instance) and so a Malloc() call may well succeed even if Malloc(-1L) fails. The other use of Malloc(-1L) is to provide the user with the total amount of free memory available. This requires a loop of such calls which means that any other program running under MultiTOS will be unable to allocate memory. An alternative method is provided by MultiTOS using a Dfree() system call to determine the amount of free 'disk space' on the drive U: where U:\PROC is the current directory. This will actually result in information about free and allocated memory being returned. During system calls, MultiTOS saves and restores the context which adds significant amounts of time to each system call. Programs making a lot of system calls run very slowly but this can be remedied with certain strategies. Making fewer calls and using functions that do as much work as possible in each call are preferable. Various BIOS functions do little work on each call. Bconout() outputs a single character, whereas a GEMDOS function such as Fwrite() can output thousands on a single call. Replacing BIOS calls with GEMDOS ones will generally speed up any program. GEMDOS functions can also have their input and output redirected to disk files, pipes and other devices and the GEMDOS interface is similar to functions calls in MS-DOS, OS/2 and UNIX making the porting of programs easier. Numerous programs, especially those using the AES, do not run entirely successfully under MultiTOS for various reasons. Some try to grab all the available memory, many use modified AES and VDI calls (or even write their own interfaces), lots use undocumented and illegal methods and many have very modal aspects preventing access to other windows, such as only using dialog boxes. However, this situation is improving quickly with the appearance of MagiC and stable releases of MiNT. MultiTOS is available for all machines, including 68000-based ones. MiNT is freely available in the public domain. However, a multitasking AES, such as v4.10, is also required to provide the full MultiTOS environment. This is only available commercially and to developers. Multi-user A computer system that allows simultaneous use by more than one person, often at remote terminals. MUPB Memory Usage Parameter Block. MW Multitos Windows. MW.PRG is a program that can be used under MultiTOS which allows multiple MiNT shells to be run in GEM windows under the standard AES. It emulates the VT52 like the ST BIOS. These windows can be moved about on the screen and several can be active, each running a separate task. A small screen font can be used enabling a full-screen TOS program to be run in a small window enabling other parts of the screen to be accessible. Another program called MGR does the same job under MiNT but MW is smaller and using the standard AES means you can run accessories along with MiNT shells. However, there are no graphics. In both cases a program can interrogate a window's size and location and can respond when the user changes the size. MW is based on UW, or UNIX Windows and written by Allan Pratt, but is PD and not a product of Atari Corporation. Production releases of MultiTOS include MINIWIN instead of MW. Mylar The DuPont trade name for the polyester film used as the substrate in floppy disks and tape. M 181 entries EOF