Paradise/Western Digital Super VGA Chips.

	       Max mem   Max 16col  256 col
    PVGA1A     512k/1M     800x600   640x480
    WD90C00    512k/1M    1024x768   800x600   also known as PVGA1B
    WD90C10    256k        640x480   320x200
    WD90C11    512k       1024x768   800x600
    WD90C2x                800x600   640x480?  LCD/plasma controller derived
					       from WD90C00 ?                   
    WD90C30    1M         1024x768  1024x768   (D-step)
    WD90C31    1M        1280x1024  1024x768   (1DW - accelerator) 

  94h (W): Setup Register     (Micro Channel)

 102h (R/W): VGA Sleep Register    (setup mode only)
 bit   0  VGA enabled if set.
     1-7  Reserved.
 Note: this register can only be accessed in setup mode.

 3C3h (W): Global Enable Register
 bit   0  VGA Motherboard Enable if set

 3C4h index  3  (R/W): Reconfigured Character Map Select
 bit 0-2  Offset of character map in plane 2/3 in 8k blocks
     3-4  Character map select from plane:
	    0: plane 2
	    1: plane 2 if attr. bit 3 set, plane 3 else
	    2: plane 3 if attr. bit 3 set, plane 2 else
	    3: plane 3

 3C4h index  6  (R/W):
      used in WD90C1x.
  
 3C4h index  7  (R/W): Display Configuration Status (WD90C1x Only)
 bit   0  (R) Monitor type
       1  (R) EGA emulation if set
       2  (R) 6845 compatibility if set
       3  (R) Color mode if set
     4-7  Scratch Pad

 3C4h index 10h (R/W):                              (WD90C11 Only)
 bit 2  (WD90C11 Only)

 3C4h index 11h (R/W): System Control Interface     (WD90C1x Only)
 bit   0  (WD90C1x Only) 16 bit access to CRTC, Graphics
	  Controller and Sequencer Registers if set
       1  (WD90c1x Only) 16 bit access to Attribute Registers if set.
	  If so 3C0h is index and 3C1h is data port.
       2  Enable Write buffer if set
     3-4  Enhanced speed depending of host bus speed:
	   0 for 12MHz, 1 for 10 MHz, 2,3 for 8 MHz
       5  Enhanced text mode operations if set
       6  Enhanced operation on blank lines if set
       7  (WD90C1x Only) If set Bank reg PR0A is used for read cycles
	and PR0B for write cycles, else PR0B is used for A000h-A7FFh
	and PR0A for A800h-AFFFh.

 3C4h index 12h (R/W): Miscellaneous Control #4      (WD90C1x Only)
 bit   6  Enable Cursor Blinking if set
       7  Enable External Sync

 3C4h index 14h (R/W):                                (WD90C30 only)
 bit 0-3

 3CEh index  9  (R/W): PR0A Address Offset A
 bit 0-6  (<WD90C30) Added to bit 12-18 of video memory address if
		     Bank A selected. (Reads if 3C4h index 11h bit 7 set,
		     A800h-AFFFh if 3CEh index Bh bit set and 64k config
		     B000h-BFFFh if 128k config. A000h-AFFFh else).
 bit 0-7   (WD90C30) same but bit 12-19 rather than 12-18.        

 3CEh index  Ah (R/W): PR0B Address Offset B
 bit 0-6  (<WD90C30) Added to bit 12-18 of video memory address if
		     Bank B selected. (Writes if 3C4h index 11h bit 7 set,
		     A000h-A7FFh if 3CEh index Bh bit 3 set and 64k config,
		     A000h-AFFFh if 128k config).
 bit 0-7   (WD90C30) Same but bit 12-19 rather than 12-18.

 3CEh index  Bh (R/W): PR1 Memory Size
 bit   0  Enable on card ROM if set
       1  Select 16 bit ROM if set
       2  Select 16 bit Memory  if set
       3  PROB enabled if set, else use PR0A for both banks
     4-5  Memory Map.  0=A000-BFFFh standard VGA,
		       1=0-3FFFFh, 2=0-7FFFFh and 3=0-FFFFFh
     6-7  Installed memory:
	    0  256k VGA standard
	    1  256k PVGA bank switching
	    2  512k do
	    3    1M do

 3CEh index  Ch (R/W): PR2 Video Configuration
 bit   0  Force VCLK (overrides SQE1 bit 3).
       1  Third Clock Select Line VCLK2
     2,5  Character Map Select/Underline
	   0  Characters are taken from plane 2
	   1  do, but characters are underlined if
	      bit 0 of the characters attribute is set.
	   2  Characters are taken from plane 3.
	   3  If bit 3 of the characters attribute is set the
	      character is taken from plane 3, else from plane 2.
     3,4  Character Clock Period Control
	   0  IBM VGA character Clock (8 or 9 dots wide).
	   1  7 dots (used for 132 character modes).
	   2  9 dots
	   3  10 dots
	  Selecting 10 dots/character modifies the horizontal PEL
	  panning register (3C0h index 13h).
       5  Character Map Select.
       6  6845 Compatibility (6845 if set, EGA/VGA if clear).
       7  AT&T/M24 Mode Enable, 400 line enable

 3CEh index  Dh (R/W): PR3 CRTC Control
 bit   0  Lock Vertical Timing
       1  Lock Prevention. Prevent locking through the Vertical
	  Retrace register (3d4h index 11h bit 7).
       2  Multiply Cursor Start, Cursor Stop, Preset Row Scan
	  and Maximum Scan Line registers by 2
     3-4  bit 16,17 of CRTC Display Start Address
       5  Lock Horizontal Timing
       6  Lock HSYNC Polarity
       7  Lock VSYNC Polarity

 3CEh index  Eh (R/W): PR4 Video Control
 bit   0  Extended 256 color Shift register Control. Configures
	  the video shift registers for extended 256 color mode.
       1  EGA compatibility. Disables reads of all registers
	  that are writeonly on the EGA, and of PR0-5.
       2  Lock internal Palette and Overscan registers
       3  Override CGA Enable Video bit.
	  Overrides the CGA "enable video" bit 3 of 3D8h
       4  Tri-state Memory Control Outputs
       5  Tri-state Video outputs
       6  PCLK=VCLK
       7  BLNK/Display Enable

 3CEh index  Fh (R/W): PR5 General Purpose Status and PR Register
 bit 0-2  Extended registers PR0-4 Unlocked if set to 5
       4  Read protect PR0-4 if set.
       7  Multisync if set, fixed frequency else.

 3d4h index 29h (R/W): PR10 Unlock PR11-17 Registers (WD90Cxx Only)
 bit 0-2  Write of PR11-18 enabled if set to 5
     3,7  Read of PR11-18 enabled if 3 clear and 7 set

 3d4h index 2Ah (R/W): PR11 EGA Switches             (WD90Cxx Only)
 bit   0  Lock 8/9 Dot Character Clock.
	  Inhibits writes to 3C4h index 1 bit 0.
       1  Lock Graphics and Sequencer Screen Control
	  Inhibits write to 3CEh index 5 bit 5-6, 3C4h index 1
	  bit 2-5 and 3C4h index 3 bit 0-5.
       2  Lock Clock Select
       3  EGA Emulation on Analog Display
     4-7  EGA Switch 1-4

 3d4h index 2Bh (R/W): PR12 Scratch Pad Register     (WD90Cxx Only)
 bit 0-7  Reserved

 3d4h index 2Ch (R/W): PR13 Interlace H/2 Start      (WD90Cxx Only)
 bit 0-7  Interlace H/2 Start. Adjusts Horizontal Sync
	  for interlace.

 3d4h index 2Dh (R/W): PR14 Interlace H/2 End        (WD90Cxx Only)
 bit 0-4  Interlace H/2 End. Adjusts horizontal Sync width
       5  Interlace enable
       6  Vertical Double Scan for EGA on PS/2 Display
       7  Enable Vertical retrace interrupts if set

 3d4h index 2Eh (R/W): PR15 Miscellaneous Control #1 (WD90Cxx Only)
 bit   0  Disable borders if set
       1  Select Display Enable Timing
       2  Enables page mode addressing in alpha modes if set
       3  Interlace comp. with 8514/A timing if set.
       4  VCLK=MCLK. If set MCLK is used for all video timings.
       5  VCLK1,VLKC2 Latched Outputs.
       6  Low VCLK. Set if VCLK is much slower than MCLK.
       7  Enable read of 46E8h

 3d4h index 2Fh (R/W): PR16 Miscellaneous Control #2 (WD90Cxx Only)
 bit   1  Standard VGA memory if set
     3-4  bit 16,17 of CRTC Address Counter Offset
     5-6  CRTC Address Counter Width
	   0= 256k, 1=128K, 2=64K

 3d4h index 30h (R/W): PR17 Miscellaneous Control #3 (WD90Cxx Only)
 bit   0  Maps out ROM at C600h-C67Fh if set
       2  (WD90C1x Only) Enables 64k ROM at C000h-CFFFh if set
       3  (WD90C1x Only) Maps out ROM at C600h-C6FFh if set

 3d4h index 32h (R/W):                               (WD90C2x Only)
 bit   0
       5  

 3d4h index 34h (R/W):                               (WD90C2x Only)

 3d4h index 37h (R/W):                               (WD90C31 Only) 
 bit 0-7  031h for the WD90C31.
 
 46E8h (R/W): Global Enable Register           (AT only)
 bit 0-2  BIOS ROM page select (8 pages of 4K each).
       3  Adapter VGA enabled if set
       4  If set the VGA is in Setup mode, where 102h and 46E8h
	  are the only ports responding.
	  Wake Up port at 102h responds only if this bit set.
 Note: This register is also addressed at 56E8h, 66E8h and 76E8h.
       Register only readable if 3d4h index 2Eh bit 7 set

    3C4h index 6 used in WD90C1x.
    3d4h index 31h-3fh used in WD90C1x.


  Bank Switching:

    Bank switching happens by adding the bank register to bit 12-19
    of the address, resulting in the window starting on a 4k boundary.

    Two different bank registers can be used either as Read/Write
    banks (WD90C1x) or as two different windows each 32k/64k big.


  Memory:

   $C000:$09  string   BIOS date 
   $C000:$35  1 byte   BIOS version 
   $C000:$7D  4 bytes  $3ED414756   ('VGA=')


  ID Paradise/WD Super VGA Chip set:

    old:=rdinx($3ce,15);
    modinx($3ce,15,$17,0);   {Lock registers}

    if not testinx2($3ce,9,$7f) then
    begin
      modinx($3ce,15,$17,5);      {Unlock again}
      if testinx2($3ce,9,$7f) then
      begin
	old2:=rdinx(base,$29);
	modinx(base,$29,$9f,$85);  {Unlock WD90Cxx registers}
	if not testinx(base,$2b) then 'Paradise PVGA1A'
	else begin
	  old1:=rdinx($3c4,6);
	  wrinx($3c4,6,$48);
	  if not testinx2($3c4,7,$f0) then 'Western Digital WD90C00'
	  else if not testinx($3c4,16) then
	  begin
	    'Western Digital WD90C2x';
	    wrinx(base,$34,$a6);
	    if (rdinx(base,$32) and 32)<>0 then wrinx(base,$34,0);
	  end
	  else if testinx2($3c4,20,15) then
	  begin  
	    if rdinx(base,$37)=$31 then 'Western Digital WD90C31'
				   else 'Western Digital WD90C30';  
	  end 
	  else if not testinx2($3c4,16,4) then 'Western Digital WD90C10'
					  else 'Western Digital WD90C11';
	wrinx($3c4,6,old1);
      end;
      wrinx(base,$29,old2);
    end;
    wrinx($3ce,15,old);
    
 

  Video Modes:

    54h  T   132   43  16  (7x9 or 8x9)
    55h  T   132   25  16  (7x9 or 8x9)
    56h  T   132   43   4  (7x9 or 8x9)
    57h  T   132   25   4  (7x9 or 8x9)
    58h  G   800  600  16  planar
    59h  G   800  600   2  odd/even  **** See note    Not on newer boards?
    5Ah  G  1024  768   2  odd/even  **** See note    Not on newer boards?
    5Bh  G  1024  768   4  packed    **** See note    Not on newer boards?
    5Ch  G   800  600 256  packed    WD90C11/3x Only
    5Dh  G  1024  768  16  planar
    5Eh  G   640  400 256  packed
    5Fh  G   640  480 256  packed
    60h  G  1024  768 256  packed         WD90c3x only
    61h  G   640  400 32k  Sierra 15bit   WD90c31 only
    62h  G   640  480 32k  Sierra 15bit   WD90c3x only
    63h  G   800  600 32k  Sierra 15bit   WD90c3x only
    64h  G  1280 1024  16  planar         WD90c31 only
    66h  T    80   50  16  (8x8)
    67h  T    80   43  16  (8x8)
    68h  G   320  200 32k  Sierra 15bit   WD90c31 only
    69h  T   132   50  16  (8x8)
    6Ah  G   800  600  16  Planar
    6Ch  G  1280  960  16  planar


    Mode 5Bh  1024x768 4 color.
      2 bit per pixel packed mode.
      Pixels start in bit 6-7.

    Mode 59h   800x600 2 color and
    Mode 5Ah  1024x768 2 color.
      One bit per pixel odd/even mode
      Pixels 0-7 are in plane 0, 8-15 in plane 1.



  Bios extensions:


----------10007E-----------------------------
INT 10 - VIDEO - Paradise VGA, AT&T VDC800 - SET SPECIAL MODE
	AX = 007Eh
	BX = horizontal dimension of the desired mode
	CX = vertical dimension of the desired mode
	     Both BX,CX in dots for graph modes, chars for alpha modes
	DX = Number of colors desired (0000h for monochrome)
Return: BH = 7Eh if successful (Paradise VGA)
	AL = 7Eh if successful (AT&T VDC800)
----------10007F-----------------------------
INT 10 - VIDEO - Paradise ....   EXTENDED MODE SET
	AX = 007Fh
	BH = 00h   set VGA operation
	BH = 01h   set non-VGA operation
		   color modes (0,1,2,3,4,5,6) will set non-VGA CGA operation
		   monochrome mode 7 will set non-VGA MDA/Hercules operation
	BH = 02h   Query mode status
		   Return: BL = 00h if operating in VGA mode, 01h if non-VGA mode
			   CH = total video RAM size in 64k byte units
			   CL = video RAM used by the current mode
	BH = 03h   Lock current mode. Allows current mode
		   (VGA or non-VGA) to survive re-boot.
	BH = 04h   Set non-VGA MDA/Hercules Mode
	BH = 05h   Set non-VGA CGA Mode
	BH = 06h   Set VGA Mono Mode
	BH = 07h   Set VGA Color Mode
	BH = 09h..0Fh   Write Paradise Register
			BL = New value of PR register
	BH = 19h..1Fh   Read Paradise Register
			Return: BL = Value of register
			BH: (Read) BH: (Write)   Register
			19h        09h          PR0A     Port 3CEh index 09h
			1Ah        0Ah          PR0B     Port 3CEh index 0Ah
			1Bh        0Bh          PR1      Port 3CEh index 0Bh
			1Ch        0Ch          PR2      Port 3CEh index 0Ch
			1Dh        0Dh          PR3      Port 3CEh index 0Dh
			1Eh        0Eh          PR4      Port 3CEh index 0Eh
			1Fh        ---          PR5      Port 3CEh index 0Fh
	BH = 20h   Emulate EGA with Analog Monitor   (WD90Cxx Chips Only)
		   BL=EGA Switches in Bit 0-3
	BH = 29h..30h   Read Paradise Register       (WD90Cxx Chips Only)
			Return: BL = Value of register
			BH:    Register:
			29h   PR10     Port 3CEh index 29h
			2Ah   PR11     Port 3CEh index 2Ah
			2Bh   PR12     Port 3CEh index 2Bh
			2Ch   PR13     Port 3CEh index 2Ch
			2Dh   PR14     Port 3CEh index 2Dh
			2Eh   PR15     Port 3CEh index 2Eh
			2Fh   PR16     Port 3CEh index 2Fh
			30h   PR17     Port 3CEh index 30h

Return: AL = 7Fh  If successful  (AT&T VDC600)
	BH = 7Fh  If valid call (Paradise/Western Digital)